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LOW POWER, LOW COMPLEXITY LEVEL SENSITIVE SCAN LATCH IN CMOS TECHNOLOGY

IP.com Disclosure Number: IPCOM000007298D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2002-Mar-12
Document File: 3 page(s) / 154K

Publishing Venue

Motorola

Related People

Nihat Cabuk: AUTHOR [+2]

Abstract

CIRCUIT DESCRIPTION This publication introduces a new Level Sensi- tive Scan Latch (LSSL) with reduced power and low gate count. The most important advantages are that the gate count is reduced by -30% and the power consumption is reduced by -80% (toggling clock only) by -50% (toggling clock and data) compared to current designs (see [l]). The reduction is larger in macros containing multiple LSSLs because there will be only one clock driver set.

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MOTOROLA Technical Developments Volume 23 October 1994

LOW POWER, LOW COMPLEXITY LEVEL SENSITIVE SCAN LATCH IN CMOS TECHNOLOGY

by Nihat Cabuk and Thomas Harms

INTRODUCTION

CIRCUIT DESCRIPTION

  This publication introduces a new Level Sensi- tive Scan Latch (LSSL) with reduced power and low gate count. The most important advantages are that the gate count is reduced by -30% and the power consumption is reduced by -80% (toggling clock only) by -50% (toggling clock and data) compared to current designs (see [l]). The reduction is larger in macros containing multiple LSSLs because there will be only one clock driver set.

  A precondition for correct mnctionality is the availability of non-overlapping control signals shown in Figure 1. Either the master gate MB or the scan gate SCB signal will be active because they are used to decide whether data or scan data will be multiplexed into the latches.

  In general, a LSSL has five circuit sections. They are the clock buffer, the input multiplexer, the mas- ter and the slave latch and the driver. The clock buffer contains three inverters to drive the internal control signals. The multiplexer which is controlled by the signals MB and SCB, selects either data D or scan data SD to be latched. The master latch is con- trolled by a master gate MB and latches the data at the output ofthe multiplexer. The slave latch is con- trolled by a slave gate SB and latches the data at the output ofthe master latch. Two inverters behind the slave stage generate the complementary output signals.

The Functionality of the LSSL is given in Table
1. As mentioned before, either MB or SCB clocks the data D or SD into the master and SB clocks it into the slave. Thus. MB olus SB and SCB ulus SB

BACKGROUND

  Level Sensitive Scan Latches (LSSL) are used in telecom applications. Non-overlapping control sig- nals are generated to guarantee secure data transfer and storage between the master and slave latches. Although, current designs have very low gate counts, there is still a need to reduce complexity and espe- cially power, since LSSLs are used in enormous amounts in integrated telecom circuits. There is a need to avoid expensive cooling methods in larger systems. The less the complexity of LSSLs, the more information can be handled in modem telecom appli- cations like SDH, ISDN etc. and the less the power consumption, the cheaper the system can be

produced.

is a reference to a sequence ofthese signals.

FIGURE 1: FUNCTlON TABLE

SD SCBplusSB Q QB MODE

X H L H NORMAL

X H H L NORMAL

L L L H SCAN

H L H L SCAN

MB plus SB

L

L

H

H

H

X H Q QB NOR.IvlAUSCAN

0 Motorola. 1°C. 1994 89

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MOZOROLA Technical Developments Volume 23 October 1994

  In the present circuits, transfer gates are used to control the storage elements. They need both the true and the complementary control signal to switch on or off. Therefore it was always previously neces-

sary to generate tr...