Browse Prior Art Database

REDUCING THE OVERALL WIDTH OF PLA STRUCTURES

IP.com Disclosure Number: IPCOM000007301D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2002-Mar-13
Document File: 3 page(s) / 132K

Publishing Venue

Motorola

Related People

James M. Sibigtroth: AUTHOR [+4]

Abstract

This article describes two new techniques that can be used to reduce the overall width of PLA struc- tures in the UDR process without modifying any process rules. These techniques were first used on a large CPU PLA in the MC68HCll design group in Oak Hill, Texas. PLA structures in the MC68HC16 and the MC68332 have also been evaluated to gain additional data on possible silicon area savings.

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MOTOROLA Technical Developments Volume 23 October 1994

REDUCING THE OVERALL WIDTH OF PLA STfiUCTlJRES

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by James M. Sibigtroth, Greg Viot, James Broseghini and Marlan Winter

  This article describes two new techniques that can be used to reduce the overall width of PLA struc- tures in the UDR process without modifying any process rules. These techniques were first used on a large CPU PLA in the MC68HCll design group in Oak Hill, Texas. PLA structures in the MC68HC16 and the MC68332 have also been evaluated to gain additional data on possible silicon area savings.

  The PLAs in question have input terms run- ning horizontally while output minterms are verti- cal metal lines. The objective of these two techniques is to reduce the overall horizontal width ofthe PLA.

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REORDERING MINTERMS

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  The first technique is illustrated in Figure 1. The top half of the figure shows the original arrange- ment with minterms numbered 0 through 3. Xs mark places where transistors (shown as boxes) on adja- cent vertical minterm lines limit the minimum width of the structure. The lower half of the figure shows the same PLA with minterms rearranged so no tran- sistors interfere with transistors on adjacent vertical minterm lines. This allows the vertical minterms to be squeezed together, reducing the overall width of the structure. The logic ofthe structure is not altered.

  A software tool was developed to automatically modify a standard Espresso file so this technique can be applied in line with the normal design process.

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Figure 1 Reordering Minterms DUPLICATION OF INPUfS

  A second technique can be used in combina- tion with the reordering of minterms to gain addi- tional savings. This second technique is illustrated in Figure 2. The upper half of the figure shows a 4 input PLA which cannot be reduced in width with the reordering technique. The lower half of Figure 2

96 0 Motorola, 1°C. 1994

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0 M MO-LA

Technical Developments Volume 23 October 1994

shows a logically equivalent PLA which allows reduc- tion of the width of the overall PLA. Input D was duplicated and run through the PLA structure as an additional horizontal line. Some of the transis- tors that were on the original input D line have been moved to the D' line to eliminate horizontal inter- ference. Again the logic of the PLA was not changed.

  The duplicate input technique is not completely free since the height ofthe PLA is increased to allow a savings in the width. The number of inputs, the number of outputs, the logic of the PLA, and...