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Browse Prior Art Database

SCANNABLE STRONG HOLD LOGIC FOR BUS CONTROL

IP.com Disclosure Number: IPCOM000007315D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2002-Mar-14
Document File: 2 page(s) / 80K

Publishing Venue

Motorola

Related People

Jose A. Lyon: AUTHOR [+4]

Abstract

This invention provides scan controllability with- out affecting timing critical signals being used as inputs to bus state machines.

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MOTOROLA Technical Developments Volume 23 October1994

SCANNABLE STRONG HOLD LOGIC FOR BUS CONTROL

by Jose A. Lyon, Rene Delgado, Jeffrey Hopkins and Michael Gladden

FIELD OF THE INVENTION

  This invention provides scan controllability with- out affecting timing critical signals being used as inputs to bus state machines.

BACKGROUND OF THE INVENTION

  Today's high-performance microprocessors and microcomputers place ever increasing requirements on the fault-coverage ofthe design to ensure quality silicon by the time it reaches the customer. As a result, scan testing is typically used to access embedded logic which is difficult to test. By follow- ing this approach, input signals can be controlled, and the output values can be observed and com- pared. There are two approaches that are typically followed:

1) Serial output data is shifted off-chip, where it

is compared bit by bit against the expected values.
2) Serial output data can be compressed on-chip using a signature analyzer, and the final sig- nature is observed upon the completion of the test.

  The ultimate goal would be to provide as much testability as possible with the least amount of sili- con without decreasing design performance. How- ever, scan cells used to control the inputs to the logic being tested typically are inserted directly in the path of input signals. As a result of the scan cell insertion, the signal can be delayed. This poses no problem as long as there is enough margin in the signal timi...