Browse Prior Art Database

LOW RESISTANCE LOCAL INTERCONNECT ON III-V INTEGRATED CIRCUITS

IP.com Disclosure Number: IPCOM000007319D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2002-Mar-14
Document File: 2 page(s) / 98K

Publishing Venue

Motorola

Related People

Bruce Bernhardt: AUTHOR [+3]

Abstract

III-V compound semiconductor integrated cir- cuits being fabricated today are at a competitive dis- advantage in circuit density and, integration scale, when compared to Si-based integrated circuits. One of the factors limiting GaAs circuits from achieving Si circuit densities is that the "lih-off' technique is still the common method of forming ohmic con- tacts to III-V devices. In 1992, we developed a method to define the ohmic contacts with an etch process. In that invention, layered structures ofNi/Ge/W or Ge/Ni/W were used for this purpose, and patterned by the combination of dry and wet etching (known as the "Etched Ohmic Process"). The ohmic con- tact resistivity using this metal scheme was below 1O-6 Q-cm2, which is suitable for integrated circuit fabrication, The sheet resistance ofthe ohmic metal was less than 1 Q/O, suggesting a highly attractive method for distributing local signals. In this inven- tion we have expanded the Etched Ohmic Process to allow ohmic contact metallization for local interconnects.

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MOTOROLA Technical Developments Volumb 23 October 1994

LOW RESISTANCE LOCAL INTERCONNECT ON III-V INTEGRATED CIRCUITS

by Bruce Bernhardt, Jaeshin Cho and Greg HarkelI

  III-V compound semiconductor integrated cir- cuits being fabricated today are at a competitive dis- advantage in circuit density and, integration scale, when compared to Si-based integrated circuits. One of the factors limiting GaAs circuits from achieving Si circuit densities is that the "lih-off' technique is still the common method of forming ohmic con- tacts to III-V devices. In 1992, we developed a method to define the ohmic contacts with an etch process. In that invention, layered structures ofNi/Ge/W or Ge/Ni/W were used for this purpose, and patterned by the combination of dry and wet etching (known as the "Etched Ohmic Process"). The ohmic con- tact resistivity using this metal scheme was below 1O-6 Q-cm2, which is suitable for integrated circuit fabrication, The sheet resistance ofthe ohmic metal was less than 1 Q/O, suggesting a highly attractive method for distributing local signals. In this inven- tion we have expanded the Etched Ohmic Process to allow ohmic contact metallization for local interconnects.

  By utilizing the ohmic contact formation proc- ess to form local interconnects, the ohmic contact area to III-V devices need not be made any larger

than is necessary to form a good ohmic contact. This process enhancement allows one form inter- connects between two ohmic contacts of the same or different devices, and/or between ohmic and gate metal of the same device or different devices. Since one can use...