IMPROVED CMOS LDD PROCESS
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2002-Mar-18
Papu Maniar: AUTHOR [+3]
We will assume the twin wells, isolation, punchthrough and Vt adjustments, gate oxide growth have been completed. Next the gate poly and its capped oxide has been etched and stopped on the gate oxide. We pick up the process at this stage.
MOTOROLA Technical Developments Volume 24 March 1995
IMPROVED CMOS LDD PROCESS
by Papu Maniar, Bich-Yen Nguyen and Jon Fitch
spacers. The drawback of this process is the use of the not well characterized and still immature LPD process.
We will assume the twin wells, isolation, punchthrough and Vt adjustments, gate oxide growth have been completed. Next the gate poly and its capped oxide has been etched and stopped on the gate oxide. We pick up the process at this stage:
1) Gate poly oxide growth
2) N- S/D Photo
3) N- S/D implant
4) N- S/D Photo strip
5) P- S/D Photo
6) P- S/D implant
7) P- S/D Photo strip
8) Gate spacer deposition (nitride)
9) Gate spacer etch (stop on oxide)
10) N+ S/D Photo
11) N+ S/D implant
12) N+ S/D Photo strip
13) N+ S/D anneal
14) P+ S/D Photo
15) P+ S/D implant
16) P+ S/D Photo strip
SELECTIVE REMOVAL OF SiO2 AND SiGe:
1. SiGe spacers can be selectively removed by either dry or wet etch:
Dry Etch: SiGe spacer can be removed in C12 based plasma etch similar to that for Si and this should provide excellent selectivity to Si02. Other dry etches for SiGe and Ge are discussed in Oehrlein et al., J. Electrochem. Sot., ~138, No. S., 1991, but the selectivites to oxide is not known.
Wet Etch: SiGe can be selectively etched rela- tive to oxide using a etch consisting of HN03 + H202 + H20 (all acids assumed to be 30% solu- tions). Specific example is discussed in Johnson et al., J. Electronic Mat. ~21, No. 8, 1992. In this exam- ple a HN03:H202:H20::1:1:5 solution at 75°C was used to etch SiGe (Ge form 0 to 55%).
The SiGe etch rate for 40% Ge in SiGe alloy was 5 to 7 A. min whereas the oxide did not etch at all in this solution. Also for this same etch the etch rate of silicon was 0.2 to 0.3 A/min which further provides protection against any damage to the active area silicon. It is believed this etch could tirther be optimized to improve the etch rate of SiGe alloy. 2. SiGe spacers could also be etched anisotropically
in the CI2 based etch.
We propose a process that eliminates 2 mask steps from the above process and also permits the tailoring of the spacer width independently to the P-channel and N-channel. This process is shown in the attached figure.
DEPOSITION OF SiGe:
The closest prior art available is discussed in Horuchi et al., IEEE Trans. Elect. Dev., ~40, No. 8., 1993.
Here the Liquid phase deposition (LPD) of Si02 process with its selectivity to photoresist is utilized to conformally deposit Si02 and form the LDD