Browse Prior Art Database

Reducing Output Buffers Bounce (ROBB)

IP.com Disclosure Number: IPCOM000007355D
Original Publication Date: 2002-Mar-18
Included in the Prior Art Database: 2002-Mar-18
Document File: 2 page(s) / 63K

Publishing Venue

Motorola

Related People

Yoked Erlich: AUTHOR [+3]

Abstract

High noises on pad chips appeared in transition time may cause a logic interfearence , Reducing the bounce noise on pad is shown by making the driver opening sensitive to the noises , and by reducing the bounce noise it is possible to use higher frequency or/and get an higher stability.

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Reducing Output Buffers Bounce (ROBB)

Yoked Erlich

Michael Priel

Sergey Sofer

Abstract

High noises on pad chips appeared in transition time may cause a logic interfearence , Reducing the bounce noise on pad is shown by making the driver opening sensitive to the noises , and by reducing the bounce noise it is possible to use higher frequency or/and get an higher stability.

Introduction

The Reducing Output Buffers Bounce (ROBB) is a predriver module designed in order to perform low Bounce. ROBB is basically designed as a solution for high Bounce which occur when using big drivers in IO design. high Bounce in IO output buffers can causes logically errors because the high noise could force the '0' logic to look as '1' logic.

Basic output buffer design (which suppose to work with 9n delay) is represented in Fig 1. while in Fig 2. the noise simulations results are shown in order to compare output buffer differences.

In Fig 3. The patent circuit is shown and the results of this simulations is shown in Fig 4.

Both the Basic output buffer example and the improved output buffer was simulated with the same terms , spice and basic enviorment structure which was simulated with 8 pins that were changed simultaneously and another two circuits which one of them is in permanent pullup state and the other one is in permanent pulldn state.

In addition 10pf - 50pf capacitor , 1nH - 6nH inductor was added in each pad in order to simulate the Load ,and the noisy supplies inductors size range was between 0.5nH - 2.5nH .

In the basic output buffer case the Bounce is very high ,about 23% of the maximum voltage value, while in the improved case the Bounce is half of the simple method value , about 10% of the maximum voltage value.

The main Patent idea is to reduce this high Bounce by the method that will be explained in the next paragraph.

The mechanism is pulling the Driver gate voltage to zero , in every time that the buffer is in pulldn mode . the pulling is stronger as much as the noise is higher .

The two transistors (M5,M7) ,that their gates are conected to 'io_d2' signal, are the main predriver components (like in the basic example) .

The pmos transistor (M5) is pushing high logic in order to open the driver nmos  (M97) .

The nmos transistor (M7) is cutting off the nmos driver ,in order to open the pmos driver .

The three transistors (M8,M63,M6) with the special connectivity are following the noisy ground signal  with Vtn (nmos threshold voltage) DC level (on 'low_voltage_pulldn' signal).

The nmos transistor (M8) is following the noisy ground.

The two pmos tra...