Browse Prior Art Database

SYNCHRONISER FOR A DATA BUS

IP.com Disclosure Number: IPCOM000007356D
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2002-Mar-19
Document File: 2 page(s) / 103K

Publishing Venue

Motorola

Related People

Michael Drozd: AUTHOR

Abstract

This device provides an asynchronous data trans- mission of parallel data with an error suppression mechanism which reduces the error probability ofa parallel bus system to the probability of a single bit data transmission.

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MOZOROLA Technical Developments Volume 24 March 1995

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SYNCHRONISER FOR A DATA BUS

by Michael Drozd

  This device provides an asynchronous data trans- mission of parallel data with an error suppression mechanism which reduces the error probability ofa parallel bus system to the probability of a single bit data transmission.

  A device connected to an asynchronous data bus captures data from the bus according to an internal time clock. During the set-up and hold time of the data capture, the data must remain constant in order to be captured without error. If the data does change during the set-up and hold time, a metastable state may occur, possibly giving rise to an erroneous data signal.

  The error probability of a parallel input register depends more on dataskew than on the set-up and hold time interval of the individual DFFs in the reg- ister. Dataskew is the time difference between the propagation delay of the slowest and the fastest bit in the bus.

  The bus synchroniser consists of one bit synchroniser for every bit. Each bit synchroniser observes the time relation between the data chang- ing edge and the clock changing edge.

Figure 1 demonstrates a bit synchronizer. Q2 is the observed D-flip-flop. It clocks the input data din

at the positive clock edge. Q4 clocks the data at the negative clock edge. QI and Q3 contribute to the observer mechanism. Q5 clocks the data at the sec- ond clock edge and outputs the synchronised data.

  At the positive clock edge, Ql stores the actual state of the input line din. A&er a time delay fd which is greater than the set-up and hold time tsu,h, Q2 stores din at the positive edge of clk0. Afier a second delay of fd Q3 stores din (positive edge of c/k& Four different behaviours ofthe circuit are possible:

  1. The output of QZ and Q3 are identical. The output of EXORI is low. The output phase signals no violation. The input select is direct connected

0 Molorola, Inc. 1995

with phase in an one-bit synchroniser. The multi- plexer MUX1 transmits the data from Q2 to the in...