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FABRICATION OF A SILICON DIOXIDE/NITRIDE MULTI-LAYER STACK AS A LOW-K DIELECTRIC FILM

IP.com Disclosure Number: IPCOM000007368D
Publication Date: 2002-Mar-19
Document File: 7 page(s) / 85K

Publishing Venue

The IP.com Prior Art Database

Abstract

The present invention relates in general to semiconductor devices and, more particularly, to integrated circuits having components formed on a low capacitance region of a semiconductor die. A low-capacitance dielectric isolation structure and method of making that maintains a low cost while producing a structure having improved surface planarity.

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Fabrication of a silicon dioxide/nitride multi-layer stack as a low-k dielectric film

The present invention relates in general to semiconductor devices and, more particularly, to integrated circuits having components formed on a low capacitance region of a semiconductor die.

Semiconductor technology continues to scale transistors to have smaller dimensions in order to provide increased functionality and a higher frequency capability.  For example, wireless communication devices often use integrated circuits that include high density digital signal processing functions on the same die as analog circuits operating at frequencies in excess of five gigahertz.

However, some integrated circuit components, such as passive devices, are not readily scalable.  These devices have relatively high parasitic substrate capacitances, which often limits the overall frequency capability of an integrated circuit.  For example, inductors are not easily reduced in size without reducing their quality factor or inductance to an unacceptable level, and bonding pads are not scalable because of the need to attach wire bonds to the bonding pads.

A variety of techniques have been tried to reduce the parasitic capacitances of passive integrated circuit components.  One such technique is to form the components over a low permittivity material.  However, current low permittivity materials are expensive, and are limited to film thicknesses that are too thin to produce a substantial reduction in parasitic capacitance, or are chemically unstable thus not suitable for many semiconductor front-end processing steps.

 Another approach is to form the components over a thick dielectric film in which are formed air gaps or voids that reduce the overall permittivity of the dielectric film. 

However, previous films made with such voids introduce substantial stress in a semiconductor substrate, which degrades the performance and reliability of the integrated circuit. Additionally, such structures have poor surface planarity, which is a detriment to subsequent processing.  Although methods exist to improve the planarity, they introduce additional steps and processing costs.  Other schemes reduce the stress by producing fewer voids or voids with only a limited volume, which has a correspondingly limited effect on parasitic capacitance.

Hence, there is a need for a low-capacitance dielectric isolation structure and method of making that maintains a low cost while producing a structure having improved surface planarity.

STEP 1

(1) Deposition of 10.5 periods of 1000A TEOS /2000A nitride.

Refer to figure 1. Starting and ending with 1000A TEOS, the entire film stack (~3um) can be deposited in a plasma-enhanced chemical vapor deposition (PECVD) system without breaking vacuum using silane-based chemistry. In this case, the deposition tool limits the silane TEOS thickness to >1000A.  Alternatively, the stack can be formed by alternating thermal nitride deposition and poly/amorphous silicon deposition, fol...