Browse Prior Art Database

KNOWN GOOD DIE TEST FOR C4 (or other) BUMPED DIE

IP.com Disclosure Number: IPCOM000007453D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2002-Mar-27
Document File: 4 page(s) / 183K

Publishing Venue

Motorola

Related People

Eric Hubacher: AUTHOR

Abstract

In recent years, there has been a significant increase in the demand for semiconductor suppliers to provide bare (unpackaged) die to assembly houses for attachment to multichip modules and directly to organic carriers (printed circuit boards). This require- ment is drawing a critical need for till hmctional electrical testing (including high and low tempera- ture conditions) and burn-in of bare die to insure assembly yields and to reduce early life reliability failures ofthe silicon.

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8 MO7VROLA Technical Developments

KNOWN GOOD DIE TEST FOR C4 (or other) BUMPED DIE

by Eric Hubacher

BACKGROUND

  In recent years, there has been a significant increase in the demand for semiconductor suppliers to provide bare (unpackaged) die to assembly houses for attachment to multichip modules and directly to organic carriers (printed circuit boards). This require- ment is drawing a critical need for till hmctional electrical testing (including high and low tempera- ture conditions) and burn-in of bare die to insure assembly yields and to reduce early life reliability failures ofthe silicon.

  There are numerous industry proposals to con- tact bare die for use in test and burn-in. Many of these incorporate temporary contacting techniques employing mechanical probes, flex circuits with bumps, photo defined circuits with gold bumps on polymer coated carriers, to name a few. Most of these proposals address the contacting of aluminum pads on bare die. However, problems exist with known technologies. For instance, in many cases bumps on the die are deformed during testing, impairing the ability to successfully reflow the die to the next level carrier. While reflow processes may repair deformed bumps, this adds cost and cycle time to the manu- facturing process. In other known processes, there is also a problem of copper dissolution into the die's solder bumps when the die is attached to a tempo- rary substrate having copper traces for testing. Fur- thermore, shear forces used to remove the die from the temporary substrate may adversely affect die per- formance after test.

SOLUTION

  A solution to many of the problems associated with existing Known Good Die (KGD) testing technologies is to utilize a solder hierarchy for attaching the die to a ceramic carrier substrate. The solder hierarchy is used in conjunction with a tem- porary ceramic substrate having copper landing pads for test purposes, similar to those used for pin grid

array (PGA) packages (Figure 1). A combination of a high melting point solder and a low melting point solder is used to join the C4 solder bump to the copper pads or traces, thereby forming a temporary electrical connection to the substrate which is eas- ily broken by a reflow operation. Since the C4 bump is composed of a high melting point solder (e.g. 3%/97% by weight Sn/Pb or like), it does not reflow during the reflow of the, low melting point solder, thus there is no damage to the bumped die.

  The copper traces on the substrate are initially covered with chrome. The chrome is patterned and etched to create openings in the chrome which expose the copper. The openings in the chrome are several mils in diameter and correspond in location to bumps on a die. The entire exposed portion for the copper traces or pads on the substrate is then tinned with a high melting point tin/lead solder by placing the substrate in a solder pot or through a solder fountain (Figure 1).

  Low melting point solder (e.g. 63/37% by weight Sn...