Browse Prior Art Database

PARTIAL DRAM REFRESH FOR REDUCED POWER CONSUMPTION

IP.com Disclosure Number: IPCOM000007466D
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2002-Mar-28
Document File: 2 page(s) / 97K

Publishing Venue

Motorola

Related People

Michael Schuette: AUTHOR

Abstract

In devices which employ DRAM memory, the energy consumed in order to maintain the contents of that memory can have a significant impact on the battery life of the device.

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8 MOlYlROLA Technical Developments

PARTIAL DRAM REFRESH FOR REDUCED POWER CONSUMPTION

by Michael Schuette

PROBLEM

mode, so that the set of rows containing data to be preserved would be fairly static.

  In devices which employ DRAM memory, the energy consumed in order to maintain the contents ofthat memory can have a significant impact on the battery life of the device.

DETAILED DESCRIPTION OF SOLUTION

SOLUTION

  Many DRAM's today have a refresh mode whereby the external refresh controller supplies a row address on the address pins and a strobe on the RAS pin. This action refreshes one row of memory cells in the DRAM. To properly refresh all cells on the DRAM, the row addresses supplied must cycle through the entire set of2N unique row addresses, where N is the number of row address lines. This procedure will ensure all data in all cells is retained if refresh is done at or above a minimum frequency.

  Not all rows in a DRAM always contain data that must be preserved. The solution proposed here then is to enhance the refresh controller to allow it to store a set ofaddresses indicating which rows it is to refresh and to allow it to selectively rel?esh only those rows. It is also proposed that a capability be added to the device, most likely in the form of solI- ware, for determining which rows of the DRAM contain data are to be preserved and loading this information into the refresh controller. This infor- mation would be updated on a periodic basis as the rows containing data to be preserved change. It is expected that this solution would be applied to a device for use when it is in a powered down/inactive

  In order to carry out the proposed solution, the example device's refresh controller is constructed as shown in Figure 1. DRAM and ROM memory chips are grouped into one block in Figure 1 labeled "Mem- ory" in order to simplify the diagram. The block labeled "Addr Reg" 3 consists of two address regis- ters: lower and upper. The contents of the lo...