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STACKED CAPACITOR FORMED BY POLY SPACER PROCESS

IP.com Disclosure Number: IPCOM000007546D
Original Publication Date: 1995-Nov-01
Included in the Prior Art Database: 2002-Apr-04
Document File: 2 page(s) / 125K

Publishing Venue

Motorola

Related People

James R. Pfiester: AUTHOR [+2]

Abstract

As the SRAM bitcell area is continually being reduced to meet the demands of higher density requirements, the ability to store enough charge for soft error protection becomes more difficult. This is especially critical for TFT-based bitcells due to their small cell size and the inability of the tfl load to respond quickly to soft-error interruptions [l]. Although stack capacitors can be used to provide additional capacitance for over-gated ttl-based SRAM bitcells [2J, integration of the stacked capacitor into an undergated m-based bitcell [3] is difhcult since the highest capacitance is formed between the tfl gate poly and an additional poly plate. In an under- gated tfi bitcell, the tl? gate poly is underneath the tll channel poly layer which significantly reduces the surface area for capacitance with another polysilicon layer positioned above the tit channel poly. Similarly, forming a capacitance between the ttl gate poly and an underlying polysilicon layer (such as the window poly layer used for Vss interconnection in the bitcell array) is difficult since a thin dielectric separation would most likely result in shorting of the tl? chan- nel poly to window poly due to the HF-preclean prior to tft channel poly depositon.

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M-ROLA ,Technical Developments

STACKED CAPACITOR FORMED BY POLY SPACER PROCESS

by James R. Pfiester and Michael J. Blackwell,

  As the SRAM bitcell area is continually being reduced to meet the demands of higher density requirements, the ability to store enough charge for soft error protection becomes more difficult. This is especially critical for TFT-based bitcells due to their small cell size and the inability of the tfl load to respond quickly to soft-error interruptions [l]. Although stack capacitors can be used to provide additional capacitance for over-gated ttl-based SRAM bitcells [2J, integration of the stacked capacitor into an undergated m-based bitcell [3] is difhcult since the highest capacitance is formed between the tfl gate poly and an additional poly plate. In an under- gated tfi bitcell, the tl? gate poly is underneath the tll channel poly layer which significantly reduces the surface area for capacitance with another polysilicon layer positioned above the tit channel poly. Similarly, forming a capacitance between the ttl gate poly and an underlying polysilicon layer (such as the window poly layer used for Vss interconnection in the bitcell array) is difficult since a thin dielectric separation would most likely result in shorting of the tl? chan- nel poly to window poly due to the HF-preclean

prior to tft channel poly depositon.

  The purpose of this~ invention is to provide a simple, insertable stack capacitor for a high-density SRAM bitcell. Although'the preferred embodiment is based on an under-gated m-based bitcell, this approach can also be used for an over-gated &based bitcell. The stack capacitor is formed along the side- wall ofthe tll gate poly which allows the top surface to act as a gate electrode for a tit channel poly film above. The idea is based on a similar approach used to define a wordline for a non-volatile memory [4]. The stack capacitor is formed by first depositing a conformal silicon film and using a reactive-ion etch to form spacers along the sidewalls of the tll gate poly layer. As shown in the figure below, the spacer etch will result in filling in between closely-spaced tfl gate poly features. If a photoresist pattern is also used prior to the stack ,capacitor etch, protruding tabs can be formed which are physically connected to the spacer features and thus allow for electrical connection to Vcc in the!,bitcell array.

STACK CAPACITOR POLY / (FORMED AS SPACER)

TFT CHANNEL POLY

Fig.1

0 Mmoroia. 1°C. ,995

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