Multi-Rail Standard Cell Architecture For Dual Voltage Circuits Or Low Power Applications
Publication Date: 2002-Apr-05
The IP.com Prior Art Database
AbstractA multi-rail standard cell architecture is provided, wherein multiple voltages can be advantageously provided to each cell, e.g. one high voltage and one low volatge.
MULTI-RAIL STANDARD CELL ARCHITECTURE FOR DUAL VOLTAGE CIRCUITS
OR LOW POWER APPLICATION
BRIEF SUMMARY OF THE INVENTION
 A multi-rail standard cell architecture is provided,
wherein one high and one low voltage can be advantageously
provided to each cell.
BRIEF DESCRIPTION OF THE RELATED ART
 In standard cell architectures, power distribution lines
can be located between rows of standard cells. Typically, a
single voltage (VDD) line and a ground (VSS) line are located on
either side of a row, thereby allowing each cell in the row to
have access to VDD and VSS.
 In integrated circuits (ICs) that use a single "high"
voltage, the power consumption can be too high, but in a single
"low" voltage the performance can be too low. Therefore, it
would be advantageous for ICs to use multiple voltages.
Specifically, critical components of the IC could use one voltage
and be at high performance whereas non-critical components of the
IC could use another voltage and be in a power-saving mode. In
this manner, both performance and power could be optimized.
 In some embodiments, one design block (which could include
a collection of cells, e.g. cells located in one or more rows) is
provided only one voltage whereas another block is provided the
other voltage. Note that some cells in an IC could be "filler"
cells, which are essentially blank spaces on the IC. However,
irrespective of filler cells, this configuration could still
require complex placement and routing to ensure each cell
received the appropriate high voltage. Moreover, this
"clustering" could significantly increase IC area.
BRIEF DESCRIPTION OF THE INVENTION
 In accordance with one feature of the invention and shown
in Figure 1, multiple voltage lines (hereinafter called "rails")
can be provided, thereby allowing each cell (shown with a red
perimeter) to access one or both of the two voltages (VDDH and
VDDL) as well as ground (VSS). In one embodiment, the voltages
can be provided using different configurations of horizontal
metal rails, which are positioned between every other row. For
example, in Figure 1, voltage VDDL (i.e. the low voltage) can be
provided using a metal 2 rail, whereas voltage VDDH (i.e. the
high voltage) can be provided using a stacked metal 1 rail, a
metal 2 rail, and vias between the two metal rails.
 The thicker, vertical lines to the left, also labeled VDDL
and VDDH, can be formed from a higher metal layer. These
vertical lines can be distributed across the IC to facilitate
more efficient power distribution. Specifically, these vertical
lines feed power from the IC pins to the VDD rails. The ground
VSS lines can be provided using either a metal 1 rail or a metal
 Figure 2 illustrates the configurations of two cells,
wherein the cell on the left is formed to receive VDDL and the
cell on the right is formed to receive VDDH. In the VDDL cell, a
metal 2 rail (indicated in heavy black outline) is connect...