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Thermal Management For Flip-Chip (C4) Backside Mechanical Contact Probing

IP.com Disclosure Number: IPCOM000007629D
Publication Date: 2002-Apr-10
Document File: 17 page(s) / 26M

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method of thermal management for flip-chip (C4) backside mechanical contact probing. Benefits include a way of controlling the temperature of all high-powered CPUs and chipsets for debug and design validation. This method also provides various temperatures to be selected to provide characterization data at both hot and cold temperatures.

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Thermal Management For Flip-Chip (C4) Backside Mechanical Contact Probing

              Disclosed is a method of thermal management for flip-chip (C4) backside mechanical contact probing. Benefits include a way of controlling the temperature of all high-powered CPUs and chipsets for debug and design validation. This method also provides various temperatures to be selected to provide characterization data at both hot and cold temperatures.

              Components of the disclosed method include the following:

•             Package clamp ‑ Clamps the package into the test board socket.

•             Thermal insert with drilled target hole ‑ Provides thermal conduction for the device under test (DUT). and a target hole to obtain access to a backside (C4) node of interest (test point).

•             Indium foil - Conforms with Si and the Thermal insert for thermal conductivity.

•             Thermal insert holder ‑ Holds the thermal insert and conducts the thermal load to the cold plate.

•             Cold plate ‑ Attaches to the Thermal Insert Holder and used as a medium to force externally controlled air, thus controlling the temperature of the DUT.

•             Mechanical probe ‑ Provides physical contact to the circuit test point, through the thermal solution, to access and obtain various electrical data from the backside.

              As C4 products are developed, thermal solutions are required to enable full debug capability. For Ebeam and Uprobe systems, access to nodes on the backside of the Si is required. The information contained in this disclosure focuses on the accessibility of these nodes through the thermal-control hardware and the geometric sizes that enable good electrical access to the nodes of a device for debug.

              Conventionally, the backside is not accessed with thermal hardware. No electrical data may be obtained above ~15 W without the risk of thermal runaway and burning up the DUT. The disclosed method focuses on the accessibility of nodes through the thermal-control fixturing hardware. This access enables mechanically probing on the backside of C4 packaged designs so that electrical data may be obtained during high-power testing while the temperature of the DUT is managed. Also, the DUT can be forced to hot and cold temperatures so that electrical data can be obtained at these varying parameters.

              With Si thinned to ~100 um, the CK1 node(s) are opened with the use of both the LCE trenching and FIB techniques for backside (thru‑Si) probing. A node designated BBCLK is accessed using an FIB trenching process. The thermal plate contacts the entire backside of the Si, using indium foil as a thermal transfer medium between the plate and actual Si. This setup enables  effective thermal management.

              An opening for the mechanical probe is required to access the target nodes. Using various sized milled holes, the correct thru‑plate hole size is  determined by collected waveform. Next, the probe is landed on Si to ensure maneuverability within the thru‑plate hole. The minimum size diameter hole is 1 mm.

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