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Page Buffer Control for High Performance Dual-Flash EEPROM Microcontroller and Method Thereof

IP.com Disclosure Number: IPCOM000007631D
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10
Document File: 2 page(s) / 7K

Publishing Venue

Motorola

Related People

Mark Weidner: AUTHOR [+2]

Abstract

Page buffer control is implemented on a microcontroller with a large embedded flash EEPROM memory unit. The page buffers are controlled by a separate Flash Bus Interface Unit to provide the customer with the flexibility to achieve maxium systems performance.

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This is the abbreviated version, containing approximately 100% of the total text.

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Page Buffer Control for High Performance Dual-Flash

EEPROM Microcontroller and Method Thereof

Page 2 of 2

Figure 1

Flash Core

Page Buffer Control Register