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Alignment Methods for Navigating Integrated Circuits from the Bulk Side of Silicon Chips

IP.com Disclosure Number: IPCOM000007635D
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10
Document File: 6 page(s) / 38K

Publishing Venue

Motorola

Related People

Daniel Boyne: AUTHOR [+2]

Abstract

Techniques are described to enable accurate navigation of an integrated circuit while viewing the IC with infrared light through the silicon substrate. The techniques involve the creation of navigation landmarks on the back surface of the silicon substrate, and the subsequent measurement of the positions of these landmarks relative to the IC's internal circuitry. The relative positions can be accurately measured using one of three techniques described herein: (1) measuring the relative positions of the centers of symmetric patterns, (2) using vernier patterns, or (3) inferring the relative positions of two diffraction gratings from diffraction patterns.

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Alignment Methods for Navigating Integrated Circuits from the Bulk Side of Silicon Chips

Daniel Boyne and Terry Garyet

Abstract

Techniques are described to enable accurate navigation of an integrated circuit while viewing the IC with infrared light through the silicon substrate. The techniques involve the creation of navigation landmarks on the back surface of the silicon substrate, and the subsequent measurement of the positions of these landmarks relative to the IC's internal circuitry. The relative positions can be accurately measured using one of three techniques described herein: (1) measuring the relative positions of the centers of symmetric patterns, (2) using vernier patterns, or (3) inferring the relative positions of two diffraction gratings from diffraction patterns.

Problem Description

Electrical failure analysis (F.A.) of integrated circuits depends on electrical measurements of the internal nodes within the IC. Accessing these internal nodes from the front side of the die has become increasingly difficult because (1) the number of interconnect layers continues to increase, and (2) advanced IC packaging schemes, such as flip-chip packages, prohibit access to the front side of the die.

As a result of these challenges, electrical characteristics of internal nodes are now measured through the substrate of high-end ICs in many F.A. labs. That is, measurements are made from the backside of the IC. Such measurements are typically performed using optical techniques, whereby the logic level of an internal node is inferred from infrared light that is the emitted or reflected from an internal semiconducting structure. Other techniques also exist, including the creation of a small hole in the substrate though which a conducting probe tip is inserted.

A fundamental problem that is unique to such backside measurements is the challenge of accurately locating the position of the circuit element of interest. These elements -- typically MOS transistors -- can have lateral dimensions of the order of 0.1 microns. Because the silicon substrate through which these structures are viewed is opaque to optical light, infrared (IR) light is used to locate internal circuit elements. The relatively long wavelength of this light (1 to 2 microns) limits the resolution such that the smallest resolvable structures are approximately 0.5 microns -- far larger than the transistors used today and in the future.

Solutions

The techniques described below involve the generation of navigation marks on the back surface of the silicon IC to improve the accuracy of locating deep-sub-micron structures within the IC. Each technique requires the following two steps:

(1.)       Creation of small topographic features on the backside of the silicon die,

(2.)       Accurately measuring the relative position between these surface features and the internal circuit elements

Upon completing these two steps, any internal circuit element can be located with high spatial accuracy using the topogra...