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Compatibility of Si-gates for Metal-Oxide Dielectrics

IP.com Disclosure Number: IPCOM000007637D
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10
Document File: 2 page(s) / 42K

Publishing Venue

Motorola

Related People

P. J. Tobin: ATTORNEY [+6]

Related Documents

1986: OTHER [+12]

Abstract

Poly-silicon compatibility issues with a metal-oxide dielectric is reported and methods to achieve better Si-gate/metal-oxide compatibility discussed. It can be generally stated that CVD silicon gates using silane (SiH4) deposited at conventional temperatures (620 °C) directly onto HfO2 resulted in films with very high leakage. However, depositing the CVD Si-gate at a lower temperature of 540 °C directly on HfO2 showed about 103 times reduction in gate leakage compared to the conventional 620 °C poly-Si/HfO2 of similar electrical thickness.

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Compatibility of Si-gates for Metal-Oxide Dielectrics

D. C. Gilmer, H. Tseng, R. I. Hegde, C. Hobbs, V. Kaushik, and P. J. Tobin

Poly-silicon compatibility issues with a metal-oxide dielectric is reported and methods to achieve better Si-gate/metal-oxide compatibility discussed.  It can be generally stated that CVD silicon gates using silane (SiH4) deposited at conventional temperatures (620 °C) directly onto HfO2 resulted in films with very high leakage. However, depositing the CVD Si-gate at a lower temperature of 540 °C directly on HfO2 showed about 103 times reduction in gate leakage compared to the conventional 620 °C poly-Si/HfO2 of similar electrical thickness. 

MOSFET devices have been aggressively scaled in order to improve performance, but the continuing push to decrease device feature size is limited by some of the physical properties of the current materials.  Current technology forecasts show that deep sub-micron device scaling will soon require SiO2 gate dielectrics be scaled to much less than 2 nm.  It is generally accepted that such scaling will lead to  increased tunneling currents from these very thin SiO2 gate dielectrics resulting in an unacceptable power consumption and decreased reliability. 

One alternative is to replace SiO2 with a metal-oxide having a higher dielectric constant that will allow the use of a thicker, and therefore less leaky, gate dielectric.  Towards this end, HfO2 has been evaluated to replace SiO2 as a gate dielectric due to its observed physical stability and calculated thermodynamic stability against silicon, and because it has a relatively high dielectric constant (~25)1 and band gap (~5.6 eV)2.  However, electrical results using MOSCAPs indicate an incompatibility of HfO2 with a conventional 620°C poly-Si gate process using SiH4.

In a conventional CMOS process, CVD poly-silicon has been the gate electrode of choice. Unfortunately, the silicon and hydrogen from the source gases can react with the metal-oxide to form a silicide, reduce the metal-oxide, or alter the composition of the interface between the metal-oxide and silicon which can degrade the electrical performance of the poly-Si/metal-oxide gate stack. To avoid the metal-oxide degradation that occurs during conventional poly-Si deposition, we propose using (1) a low temperature deposition process, (2) a process with low levels of hydrogen, or (3) a low temperature process with low levels of hydrogen.  Examples of such processes include: JVD3, ALD4, PECVD5, UV-assisted CVD6, Hot wire/CAT-CVD7, Evaporation8, MBE9, electrochemical / electrodeposition10, PVD11, hydrogen free precursors (such as SiI4)12, and precursors with a Si/H ratio lower than SiH4 (such as Si2H6, or Si3H8). 

Thus, to circumvent the poor electrical results observed with the conventional 620 °C ...