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A Quantitative, Fast and Cost Effective Method for Finding P-Slip Free Offset

IP.com Disclosure Number: IPCOM000007642D
Publication Date: 2002-Apr-10
Document File: 8 page(s) / 2M

Publishing Venue

The IP.com Prior Art Database

Related People

Brad Halleck: INVENTOR [+2]

Related Documents

NA: OTHER [+3]

Abstract

Slip tuning has often been time consuming and costly. A quantitative and cost effective method for finding a P- slip free temperature offset in about an hour has been demonstrated. It is based on the Arrhenius equation of the temperature dependence of growth rate of silicon epitaxy. The method begins with depositing epitaxy films on P+ wafers at two different temperatures in a surface reaction controlled temperature region. For Trichlorosilane (TCS) the surface reaction controlled temperature region is below 1000°C. Other silicon source gases maybe used to obtain similar results. The film thickness of the resulting two P+ wafers is measured in locations in close proximity to the center, front, side, and rear thermocouples, and is then used to determine the apparent activation energy. With the knowledge of the apparent activation energy and based on the thickness difference, one is able to calculate the temperature difference, i.e., offset, between the center location and the edge locations (front, side, and rear). For higher temperature applications, the calculated offset needs to be adjusted by subtracting an empirical constant to take into account the difference in heat loss between the edge and the center of the wafer. The offset is then verified by processing a P-wafer, and can be expanded to obtain a slip free window. It is therefore feasible to use just two P+ wafers to determine slip free offsets for the front, side and rear zones, and one P- to verify the slip performance. The entire process of finding a P- slip free offset can be completed in about one hour at an expense of three wafers.

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