Browse Prior Art Database

Mechanism to Enhance Performance on DRAM DDR Interface by Separating Data Sampling

IP.com Disclosure Number: IPCOM000007643D
Original Publication Date: 2002-Apr-10
Included in the Prior Art Database: 2002-Apr-10
Document File: 1 page(s) / 27K

Publishing Venue

Motorola

Related People

James Andrew Welker: AUTHOR

Abstract

This proposal describes a mechanism for separating the sampling of positive and negative edge captured data from a FIFO. The important components of this design include a DDR interface. In addition, a receive structure using a FIFO with programmable sample points is needed in the design for this invention. This invention improves performance by optimizing the data sampling.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 78% of the total text.

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0//EN"><DIV> </DIV><DIV>Mechanism to Enhance Performance on DRAM DDR Interface by Separating Data Sampling

James Andrew Welker

Abstract</DIV><DIV>

</DIV><DIV>This proposal describes a mechanism for separating the sampling of positive and negative edge captured data from a FIFO.  </DIV><DIV>The important components of this design include a DDR interface. In addition, a receive structure using a FIFO with programmable sample points is needed in the design for this invention.  This invention improves performance by optimizing the data sampling.

Body</DIV></DIV><DIV>BBBBB

<DIV>When the controller for a DDR interface is sampling data based on a fixed sample point, it can be set up to sample the positive and negative edge data separately. The best performance for sampling the data can be obtained by sampling the positive edge data separate from the negative edge data. This will optimize the read latency for single data beat reads. This can be accomplished by maintaining `last_cycle' and `mid_cycle - 1' signals. `Last_cycle' will be asserted when the current core clock is the last core clock within the current DRAM applied clock. With a clock ratio of 8:1, `last_cycle' would be core cycle 7, whereas `mid_cycle - 1' would be core cycle 3. Two small counters can be used to separate the positive edge and negative edge data sampling. The 1st counter will be reset on `last_cycle' (so it will output a value of 0 on `first_cycle'), and the 2nd count...