Browse Prior Art Database

LAYOUT SCAN INSERTION AND SCHEMATIC BACKANNOTATION FOR AT SPEED TEST

IP.com Disclosure Number: IPCOM000007698D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-16
Document File: 5 page(s) / 174K

Publishing Venue

Motorola

Related People

Tron Womack: AUTHOR [+2]

Abstract

A full-scan microprocessor architecture requires connecting every flip-flop in the design together into a serial shill register by daisy chaining the scan data output of one flip-flop (SDO) to the scan data input (SDI) of the next flip-flop. These connections make up the scan chain. At speed testing of such archi- tecture requires efficient connection ofthe scan chains based on the final flip-flop locations, and the ability to reflect or backannotate the scan chain connectivity into the original design schematics for verification.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 47% of the total text.

Page 1 of 5

MmROLA Technical Developments

8

LAYOUT SCAN INSERTION AND SCHEMATIC BAC~NNOTATION

FOR AT SPEED TEST

by Tron Womack and Fernando Torre

BACKGROUND

  A full-scan microprocessor architecture requires connecting every flip-flop in the design together into a serial shill register by daisy chaining the scan data output of one flip-flop (SDO) to the scan data input (SDI) of the next flip-flop. These connections make up the scan chain. At speed testing of such archi- tecture requires efficient connection ofthe scan chains based on the final flip-flop locations, and the ability to reflect or backannotate the scan chain connectivity into the original design schematics for verification.

  Previously, problems have been encountered in designing the scan chain. When an automated sys- tem is used, the scan chain is connected before the flip-flops are placed in the layout. The placement of the flip-flops is performed to most efficiently use the substrate, but not necessarily the metal layer. As shown in Figure 1 on page 3, the automated system has a lot of complicated connections and may require more than one interconnect level. Alternatively, the placement of the flip-flops may be made before the scan chain is created with a human making the scan chain connections after placement. This latter approach is time consuming, with possible errors including layout not matching the schematic.

SCAN DATA INSTANCE ORDER GENERATION FROM INITIAL CELL PLACEMENT

  A new method of automatically forming a layout without the problems of the prior art has been devised. In this method, the flip-flops are placed in or on the substrate before the scan chain connec- tions between the flip-flops are defined. Afier cells have been placed in a standard cell block, ignoring the connections between SD0 and SD1 pins of the flip-flops, the scannable instance locations are extracted and manipulated to generate a tile containing the scan chain instance order. This order is based on closest neighbor in a user definable ver- tical or horizontal raster pattern, depending on the

aspect ratio and expected routing congestion. To reduce routing congestion the scannable instances are oriented in such a way that the SD0 terminal in a cell is adjacent to an SD1 terminal in the next cell in the chain. The output file contains the scan chain cell and instance names in the right sequence so as to minimize routing wire length. Instance names contain hierarchical information extracted from the initial hierarchical netlist. This information is used during schematic backannotation.

  A standard cell block may contain more than one chain, as is the case !in parallel scan testing. In this situation, multiple scan chain order files are automatically generated ,based on a user provided chain length. Each lile contains the chain input and output terminal names, and the scan chain cell and instance names. Figure 2 on page 4 shows both, the horizontal and vertical scan chain ordering schemes. Figure 2 only s...