Browse Prior Art Database

Method for multi-stack wafer-level packaging

IP.com Disclosure Number: IPCOM000007708D
Publication Date: 2002-Apr-16
Document File: 7 page(s) / 72K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for multi-stack wafer-level packaging (MS-WLP). Benefits include simplified manufacturing process and improved performance.

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Method for multi-stack wafer-level packaging

Disclosed is a method for multi-stack wafer-level packaging (MS-WLP). Benefits include simplified manufacturing process and improved performance.

Description

              The disclosed method includes one die positioned at the bottom of a stack of multiple dice (see Figure 1). The second die and the rest of the stack dice must be equal in size or smaller in width than the largest die, which must be at the bottom of the stack. Length must be less than the bottom die. The short space serves as a routing area for the interconnect. Wire bonding, molding process, and the use of substrate in packaging assembly are eliminated. The disclosed package design has a small footprint (see Figure 2). The design is flexible for stacking multiple dice.

              Major components of the disclosed method are:

§         Die (silicon)

§         Dielectric (polyimide)

§         Redistribution (copper/aluminum/conductive polymer)

§         Solder ball/bump (lead free), 96.5Sn-3.5Ag

§         Under-bump metallization (UBM), Ni/Au

Advantage

              The disclosed method provides advantages, including:

§         Minimal footprint

§         No underfill at board mounting

      -             Does not require wire bonding interconnect

              -             Does not require substrate in the package assembly

              -             Does not require molding process in packaging

              -             Minimized IC to PC board inductance

      Die and package are manufactured and tested on the wafer prior to singulation.

Detailed description

              The disclosed method includes the following process steps:
1.           Deposition: Dielectric polyimide (Pi) material in green color deposited into a wafer                 surface (see Figure 2)
2.           Laser cut: Removal of Pi-1 to expose die pad for the first copper (Cu) trace layout                interconnect (see Figure 3)
3.           Metallization: Deposition of Cu material into the selected cut trace area (see Figure 4)

4.           Deposition: Deposition of Pi-2 to cov...