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Method for a compliant interconnection using an edge ring for chip attachment

IP.com Disclosure Number: IPCOM000007710D
Publication Date: 2002-Apr-16
Document File: 2 page(s) / 86K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a compliant interconnection using an edge ring for chip attachment. Benefits include improved productivity, improved reliability.

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Method for a compliant interconnection using an edge ring for chip attachment

Disclosed is a method for a compliant interconnection using an edge ring for chip attachment. Benefits include improved productivity, improved reliability.

Background

              Coefficient of thermal expansion (CTE) mismatch of a substrate to a die transfers stress to inter-layer dielectric (ILD) material. Low- and lower-strength ILDs cannot accommodate the stresses. Conventionally, solder bumps are used between the die and the package (see Figure 1). However, the problem has not been solved for weaker ILD materials, especially when Cu is used as the bump material on the die.

      Compliant interconnections with solder have been successfully fabricated. Anodic bonding has also been used to successfully join interfaces.

Description

              The disclosed method is an interconnection scheme that provides for a compliant interconnection to compensate for die/substrate CTE mismatches in combination with a method for holding the die and package together.

              The key elements of the method include:

§         The die side has a compliant interconnection.

§         A bondable ring is created around the outer edge of the die.

§         The die is held in place against the substrate using a bonding method to attach the bondable ring to the substrate.

Advantages

              The stresses from the CTE mismatch between the substrate and the die are accommodated by the compliance of the interconnection. No solder or adhesives are required on the individual connections. No UF...