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Method and Apparatus to Design and Physically Optimize Scan Wrapper for SOC DFT

IP.com Disclosure Number: IPCOM000007717D
Original Publication Date: 2002-Apr-16
Included in the Prior Art Database: 2002-Apr-16
Document File: 9 page(s) / 67K

Publishing Venue

Motorola

Related People

Anil Patel: AUTHOR [+2]

Abstract

Scan chains are traditionally formed in the logical domain to address design for testability concerns, very early in the design flow. Such a design or Intellectual Property (IP) block needs a scan wrapper due to the following reasons; to make multiple scan chains configurable for DFT of System on Chip (SOC) design; to isolate testing of an IP block during testing of the other blocks; to reuse functional vectors for the IP block on a tester for hierarchical AC scan. The wrapper design is generally build according to logical I/O pin order and may use shared I/O scan wrapper cell design. Such kind of traditional scan wrapper design method creates routing congestion due to the fact that the logical I/O pin order may differ with the physical I/O pin order. This method solves the problem of developing scan wrappers for SOC designs, by automatic synthesis and optimization of scan wrapper designs using physical placement information in addition to logical information. As a result it reduces the routing congestion, die size and power consumption of a design, while improving signal integrity and timing performance for both functional operation and AC/DC scan operation.

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Method and Apparatus to Design and Physically Optimize Scan Wrapper for SOC DFT

Authors: Anil Patel, Jerome Hannah

Abstract:

Scan chains are traditionally formed in the logical domain to address design for testability concerns, very early in the design flow. Such a design or Intellectual Property (IP) block needs a scan wrapper due to the following reasons; to make multiple scan chains configurable for DFT of System on Chip (SOC) design; to isolate testing of an IP block during testing of the other blocks; to reuse functional vectors for the IP block on a tester for hierarchical AC scan.  The wrapper design is generally build according to logical I/O pin order and may use shared I/O scan wrapper cell design.

Such kind of traditional scan wrapper design method creates routing congestion due to the fact that the logical I/O pin order may differ with the physical I/O pin order.

This method solves the problem of developing scan wrappers for SOC designs, by automatic synthesis and optimization of scan wrapper designs using physical placement information in addition to logical information. As a result it reduces the routing congestion, die size and power consumption of a design, while improving signal integrity and timing performance for both functional operation and AC/DC scan operation.

Definitions:

Definition 1. Scan Chain

A scan chain is formed by connecting a set of sequential elements (e.g. Flip/Flop or shift register latch) in a design as a shift register chain. A modern VLSI chip can have multiple scan chains to reduce testing application time and hence testing cost.

Definition 2. IO Scan Wrapper

A Scan wrapper provides the capability to perform DFT scan testing of both the IP core and the external periphery circuitry. Using the scan wrapper, scan patterns can be generated to individually test the core IP, the external periphery circuitry, or both together.  The scan wrapper can provide greater flexibility of the embedded testing of the IP by re-configuring the length of the scan chains of both the IP core and the wrapper itself. This is referred to as a re-configurable scan wrapper.

Scan wrappers generally support the following DFT testing modes:

·        Normal functional mode

·        Core scan test mode

·        Peripheral scan test mode

·        Burn-in test mode

The normal functional mode is for the normal functional operation of a device. In this mode the wrapper scan chains are not enabled and the wrapper design functions as a simple pass through.

The IP core scan test mode is used to test the internal IP core circuitry. The internal and wrapper scan chains are used in this mode and can be configurable by a "scan chain length" variable.

The peripheral scan test mode is used to test the chip circuitry external to IP core. Here wrapper scan chains are used to test the external circuitry. In this mode the wrapper scan chain lengths are configurable by the "scan chain length" variable.

In the burn-in test mode, all of the scan chains are connected together to create...