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A METHOD FOR QUALIFYING INSTRUCTION LINE PREFETCH WITH A LINE-WRAPPED CACHE

IP.com Disclosure Number: IPCOM000007721D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-17
Document File: 3 page(s) / 142K

Publishing Venue

Motorola

Related People

Ronny L. Arnold: AUTHOR [+3]

Abstract

In a microprocessor utilizing a memory cache which contains executable instructions, a fetch of an instruction not currently located in the cache can result in idle clock cycles while a load for the instruction is requested from a lower-level cache or memory sub-system. Instruction load requests may be initiated early, as a prefetch load, by assuming an instruction flow such as sequential addresses, thus eliminating some idle clock cycles. There is, though, the problem of requesting a load for a line already held in the cache. If this occurs any lower-level caches and the memory system may be unnecessarily employed, potentially delaying service of data load/store transactions or instruction fetch misses outside the assumed instruction flow. In order to prevent redundant prefetches, it is necessary to ver- ily that a prefetch line is not resident in the cache before the prefetch load request is issued. However, cache utilization will usually preclude expending cache cycles to determine prefetch address residency.

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Technical Developments

A METHOD FOR QUALIFYING INSTRUCTION LINE PREFETCH WITH A LINE-WRAPPED CACHE

by Ronny L. Arnold, Terence M. Potter and Paul C. Rossbach

are made only for instructions not already contained in the ILl.

PROBLEM DESCRIPTION

  In a microprocessor utilizing a memory cache which contains executable instructions, a fetch of an instruction not currently located in the cache can result in idle clock cycles while a load for the instruction is requested from a lower-level cache or memory sub-system. Instruction load requests may be initiated early, as a prefetch load, by assuming an instruction flow such as sequential addresses, thus eliminating some idle clock cycles. There is, though, the problem of requesting a load for a line already held in the cache. If this occurs any lower-level caches and the memory system may be unnecessarily employed, potentially delaying service of data load/store transactions or instruction fetch misses outside the assumed instruction flow. In order to prevent redundant prefetches, it is necessary to ver- ily that a prefetch line is not resident in the cache before the prefetch load request is issued. However, cache utilization will usually preclude expending cache cycles to determine prefetch address residency.

IMPLEMENTATION

  The block diagram which follows shows the pro- posed IL1 cache and control. The cache Array block contains storage, tags, tag compare logic, and multiplexing control logic fed by the tag compare results. The Instruction Miss Queue (IMQ) contains address storage for load requests outstanding from the lower-level caches and external memory. The Cache Reload Buffer (CRB) contains tags and stor- age for serviced load requests, and is used to stage reloads to the ILl. Instructions in this system are always single-word (4 bytes) and have a word-aligned address, though that is not necessarily required for this invention.

  Note that the IL1 is logically divided into even- line and odd-line sub-arrays for both tags and actual storage. This allows both the target and wrap line storage and tags to be accessed and utilized during the same cycle. A wrap occurs when the starting word address of a 4-word fetch indexes word 5,6, or 7 of an &word (numbered O-7) line. For example, if the fetch address ends in.. .lOlOO, the starting word is word 5, and the 4-instruction fetch would return words 5,6, and 7 ofthe target line, as well as word 0, of the wrap line should tag matches occur for both lines. Since the Array shown has 2-way set associativ- ity, tags from both sets must be evaluated for both the target and wrap lines. Hits for target and wrap lines can occur in any combination ofsets.

  Once tag comparison results have been estab- lished during a fetch, the need to initiate load requests from lower-level caches or memory can be deter- mined. If a fetch target line is not present in either set of the cache Array, a load request will normally be issued for that cache line. If the wrap li...