Browse Prior Art Database

INTERRUPT ACKNOWLEDGE CYCLE PROTOCOL FOR INTEGRATED MODULES OF EMBEDDED MICROPROCESSOR SYSTEMS

IP.com Disclosure Number: IPCOM000007731D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2002-Apr-17
Document File: 2 page(s) / 99K

Publishing Venue

Motorola

Related People

Nancy Woodbridge: AUTHOR [+4]

Abstract

Wrthin integrated microprocessor based devices, it is desirable to provide an internal bus protocol that allows individual functional blocks to be developed, verified and integrated as independent modules. The internal bus protocol employed should allow each module to have: rupt acknowledge cycle protocol solves the above problems for an integrated device with centralized interrupt control.

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Page 1 of 2

MOTVROLA Technical Developments

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INTERRUPT ACKNOWLEDGE CYCLE PROTOCOL FOR INTEGRATED MODULES OF EMBEDDED MICROPROCESSOR SYSTEMS

by Nancy Woodbridge, Thomas Volpe, Donald Tietjen and Terry Biggs

  Wrthin integrated microprocessor based devices, it is desirable to provide an internal bus protocol that allows individual functional blocks to be developed, verified and integrated as independent modules. The internal bus protocol employed should allow each module to have:

rupt acknowledge cycle protocol solves the above problems for an integrated device with centralized interrupt control.

  The system architecture employing centralized interrupt control for integrated embedded micro- processor systems is shown in Figure 1. With this architecture, interrupt control and arbitration is han- dled by the system bus controller (SBC). An interrupting module may provide an individual inter- rupt request line (INT) ,to the SBC for each of its interrupt sources. The priority and autovector fea- tures of each interrupt are programmable via regis- ters in the system bus controller.

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n number of interrupts

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n number ofinterrupt vectors

CPU interrupt priority level independent of module interrupt number.

The following interrupt architecture and inter-

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Fig. 1 Centralized System Architecture for Internal Interrupt Control

0 Mx'rola. 1°C 19% 176 May 1996

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MOlVROLA Technical Developments

  The SBC decodes all active interrupt requests and drives the highest priority pending interrupt level to the internal core on the interrupt priority level lines (IPL[Z:O]). During an interrupt acknowledge cycle initiated by the core, the system bus controller decodes the interrupt level being acknow...