Browse Prior Art Database

STRUCTURES FOR ELECTROMIGRATION RELIABILITY TESTING OF ULSI DEVICES

IP.com Disclosure Number: IPCOM000007751D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-19
Document File: 3 page(s) / 172K

Publishing Venue

Motorola

Related People

Chii-Chang (Charles) Lee: AUTHOR [+2]

Abstract

As the feature size of the ultra large scale inte- gration (ULSI) devices shrinks, the importance of having a reliable via structures increases. Electromi- gration (EM) has been found in the past to be a serious cause of failure in Al interconnect. Many methods were adopted to improve the EM reliabil- ity of the interconnect. Many times, an incorrect test structure leaded the costly experiments to a totally wrong conclusion. The recently published paper(i) is a testament to the problems faced when using improper structures to acquire data. If the data and models are an artifact of the test structure, the design rules generated from such structures result in over design and increased cost of chips. This cost factors into all products and the result is tremen- dous increase in processing cost. lhis is very inefficient.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 39% of the total text.

Page 1 of 3

0 M

MO7VROLA Technical Developments

STRUCTURES FOR ELECTROMIGRATION RELIABILITY TESTING OF ULSI DEVICES

by Chii-Chang (Charles) Lee and Mark G. Fernandes

PURPOSES

  As the feature size of the ultra large scale inte- gration (ULSI) devices shrinks, the importance of having a reliable via structures increases. Electromi- gration (EM) has been found in the past to be a serious cause of failure in Al interconnect. Many methods were adopted to improve the EM reliabil- ity of the interconnect. Many times, an incorrect test structure leaded the costly experiments to a totally wrong conclusion. The recently published paper(i) is a testament to the problems faced when using improper structures to acquire data. If the data and models are an artifact of the test structure, the design rules generated from such structures result in over design and increased cost of chips. This cost factors into all products and the result is tremen- dous increase in processing cost. lhis is very inefficient.

  Traditional EM test structures, e.g. those suggested by NIST(*), which are generally followed by industry, including Motorola, are either ended with bigger stripes that lead to bond pads or ended with W-plug vias and then connected to other stripes that lead to bond pads, In the former case, the big- ger stripe at the ends of the test structures will pro- vide extra metal atoms for EM process at the cath- ode end (a metal reservoir) and provide extra vacancies at the anode end (a metal sink). Also, joule heat generated at the test structures will be conducted away efficiently by the bigger stripes at the ends to the big heat sink, the bond pads, and cause abnor- mal temperature gradient at the testing devices. This temperature gradient will drive atoms to migrate in the same and/or reverse direction of the EM proc- ess. In the latter case, the metal reservoir and metal sink effects were solved by putting down the end W-plug vias. This test structure is closer to the real circuit. However, the higher resistivity of W than Al causes excessive heating at the end vias and ther- mal gradients at the first and last vias connected to the bond pads. This phenomenon shows up seriously when the current density is higher than 2E6 A/cm2

and basically prevents performing fast EM testing or wafer level EM testing that require extremely high current density.

  Therefore, a new structure for testing the integrity/quality of a metallization is described below. The goals ofthe new structure are to solve the prob- lems of: I) material drifl due to large thermal gradi- ent, 2) abnormal material sources and sinks, 3) the stress effect due to the thermal gradient, and 4) inac- curate data which can lead to the wrong orientation for developing materials for next generation devices. The brief description that describes the basic idea is followed by a elaborate detailed description of the invention,

BRIEF DESCRIPTION

  The structure is designed such that there is no abnormal reservoir (...