Browse Prior Art Database

A NOVEL METHOD OF MINIMIZING PRINTED WIRE BOARD WARPAGE

IP.com Disclosure Number: IPCOM000007763D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-22
Document File: 6 page(s) / 258K

Publishing Venue

Motorola

Related People

Steven M. Scheifers: AUTHOR [+2]

Abstract

A method was developed to counter board warpage created by attaching die, die packages, encapsulants, and other SMT attachments to the printed wire board. The method involves applying a thin plastic coating to the underside ofthe device or attachment. The applied material will expand and contract during thermal cycling to counter the warpage generated by attachments to the printed wire boards. The method was shown to signiEcantly increase ther- mal shock reliability ofthe attached devices.

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Technical Developments

A NOVEL METHOD OF MINIMIZING

PRINTED WIRE BOARD WARPAGE

by Steven M. &heifers and Daniel Ft. Gamota

ABSTRACT

EXPERIMENTAL

  A method was developed to counter board warpage created by attaching die, die packages, encapsulants, and other SMT attachments to the printed wire board. The method involves applying a thin plastic coating to the underside ofthe device or attachment. The applied material will expand and contract during thermal cycling to counter the warpage generated by attachments to the printed wire boards. The method was shown to signiEcantly increase ther- mal shock reliability ofthe attached devices.

INTRODUCTION

  The construction of operational circuits on printed wire boards (PWB) requires the attachment of bare die, chip carriers, and supporting surface mount pas- sives as well as the application of encapsulant mate- rials over and under some devices. These devices attached to the PWB structure cause the board to warp due to the differences in the coefficients of ther- mal expansion between the devices and the board. This warpage could be minimized by either making the board thicker or more rigid by increasing the elastic modulus. Modifying the substrate thickness of a portable product or PCMCIA card incurs both a height and a weight penalty which will directly affect the types of components which may be used. Changing the modulus usually entails selecting an alternative material for the PWB construction; this option may not be feasible due to an increase in cost or other considerations. Alternatively, a thin plastic coating having an appropriate CTE can be coated opposite the devices to minimize warpage. This technique will result in a lighter weight board
(i.e., versus use of a thicker board) and does not necessarily increase the height of the board as much as thickening the board. Results of this approach are presented below.

  The test vehicles were FR4 substrates with six sites for continuity silicon test die (0.258" x 0.261", 84 I/O). The bumps on the silicon die were 97Pb/3Sn and the board bumps were 63Pb/37Sn. The solder interconnects were formed by dispensing a no clean flux onto the board die sites, followed by the place- ment of the die, and subjecting the populated FR4 board to the standard FCOB/SMT temperature pro- file in a reflow oven. After the reflow process, the assemblies were evaluated for electrical continuity and placed into a BlueM convection oven for a period of 30 minutes at a temperature of 130°C to remove physisorbed moisture before underElling the die. Once the bakeout time had elapsed, the boards were removed and the Dexter Eip chip encapsulant FP4510 was dispensed to under611 the die. Next, the boards were placed into a BlueM oven preheated to 150°C for a period of 60 minutes to cure the encapsulant. Three experimental lots of boards were fabricated, one control lot and two experimental lots. The con- trol lot had encapsulant material only under the die (Fi...