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A 32-BIT STATIC CMOS CARRY-LOOK-AHEAD STRUCTURE OPTIMIZED FOR ENERGY AND PERFORMANCE

IP.com Disclosure Number: IPCOM000007766D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-22
Document File: 4 page(s) / 249K

Publishing Venue

Motorola

Related People

Jeff Maguire: AUTHOR

Abstract

The energy ofa digital CMOS circuit is given by E = 1/2CV2, where C is the loading capacitance being switched and V is the amount ofvoltage swing. By looking at this equation, the best way to reduce the energy consumption is to reduce the voltage swing, due to its squared relationship. For static CMOS, this amounts to the reduction of the supply voltage, since it is expensive to build a circuit with voltage swings less than the supply voltage for large combinational circuits. Limited voltage swings become even more difficult when operating a cir- cuit with a supply voltage close to the threshold voltage ofthe transistors. Additionally, as the supply voltage is reduced toward the threshold voltage of the transistors, the delay through a.gate becomes more sensitive to the gate's transistor stack height due to the body effect of the transistors. Therefore, stack height of a gate can be an important constraint with low voltage design.

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M-LA Technical Developments

A 32-BIT STATIC CMOS CARRY-LOOK-AHEAD STRUCTURE OPTIMIZED FOR ENERGY AND PERFORMANCE

by Jeff Maguire

BACKGROUND

  The energy ofa digital CMOS circuit is given by E = 1/2CV2, where C is the loading capacitance being switched and V is the amount ofvoltage swing. By looking at this equation, the best way to reduce the energy consumption is to reduce the voltage swing, due to its squared relationship. For static CMOS, this amounts to the reduction of the supply voltage, since it is expensive to build a circuit with voltage swings less than the supply voltage for large combinational circuits. Limited voltage swings become even more difficult when operating a cir- cuit with a supply voltage close to the threshold voltage ofthe transistors. Additionally, as the supply voltage is reduced toward the threshold voltage of the transistors, the delay through a.gate becomes more sensitive to the gate's transistor stack height due to the body effect of the transistors. Therefore, stack height of a gate can be an important constraint with low voltage design.

  The amount that the supply voltage can be reduced also depends on the required time to finish the computation. The computation time of the cir- cuit can be most effectively reduced by restructuring the computation of the circuit, pipelining, and/or parallelism. Pipelining can be costly due to latency stalls on dependencies, and extra energy consump- tion due to additional latch overhead. Parallelism can result in work that will be thrown away (wasted computation) and higher switching activity due to data mixing during muxing. Even though pipelining and parallelism were not used in this design, these techniques could be applied very easily.

  By reducing the capacitance of the circuit, the energy consumption can be reduced linearly. This capacitance can be reduced by reducing the transis- tor sizes and the wire length of the signals. Transis- tor sizing techniques can be applied to reduce the size of the transistors without impacting the delay through the circuit. The structure of the carry chain

can impact both the size of the transistors as well as the wire capacitance ofthe circuit. It should also be stated that increase in transistor sizing can result in a reduction of the supply voltage, resulting in net linear win in terms of energy consumption. This effect is limited in adder carry chains due to the fanout loading on most of the gates of the chain. Thus a slight increase in transistor sizing can result in much larger loading capacitances on the previous gate stage.

  Energy consumptions can be reduced in a third way by reducing the switching activity of the cir- cuit. Dual Pass Logic (DPL) has become a popular logic family. However DPL requires that gates be built to produce both the true and complement of a signal which both have to be routed creating more routing capacitance. This also results in more rout- ing congestion, increasing the size of the circuit. Dyna...