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A MULTIBIT SIGMA DELTA ADC ARCHITECTURE

IP.com Disclosure Number: IPCOM000007767D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-22
Document File: 2 page(s) / 105K

Publishing Venue

Motorola

Related People

Michael R. May: AUTHOR

Abstract

Multibit quantizers in sigma delta analog to dig- ital converters increase the achievable SNDR by reducing the quantization noise power by approxi- mately 6dB/bit. However, when a multibit quantizer is used in the feedback loop of a classic sigma delta ADC, the multibit DAC that generates the feedback signal must be very linear. In fact, the linearity of the DAC must exceed the SNDR specification of the entire sigma delta ADC, since nonlinearities in the DAC will show up at the input and degrade per- formance as if the input signal was sampled in a non linear fashion. The linearity requirement on the DAC effectively excludes multi-bit quantizers from generating the feedback signal that is subtracted horn the input signal. Several architectures have been developed to sidestep the DAC linearity requirement while realizing significant performance improvement from the multi-bit quantizer. The most popular is a cascade of modulators, often referred to as a MASH architecture.

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MolylRoLA Technical Developments

A MULTIBIT SIGMA DELTA ADC ARCHITECTURE

by Michael Ft. May

  Multibit quantizers in sigma delta analog to dig- ital converters increase the achievable SNDR by reducing the quantization noise power by approxi- mately 6dB/bit. However, when a multibit quantizer is used in the feedback loop of a classic sigma delta ADC, the multibit DAC that generates the feedback signal must be very linear. In fact, the linearity of the DAC must exceed the SNDR specification of the entire sigma delta ADC, since nonlinearities in the DAC will show up at the input and degrade per- formance as if the input signal was sampled in a non linear fashion. The linearity requirement on the DAC effectively excludes multi-bit quantizers from generating the feedback signal that is subtracted horn the input signal. Several architectures have been developed to sidestep the DAC linearity requirement while realizing significant performance improvement from the multi-bit quantizer. The most popular is a cascade of modulators, often referred to as a MASH architecture.

  A MASH architecture is a cascade of independ- ent sigma delta noise shaping loops, with the nth stage having as its input some function ofthe (n-1)th stage quantizer input and output. The outputs of

each of the noise shaping loops are then filtered digitally and summed to obtain the output of the sigma delta MASH ADC. In this way, most of the quantization noise of all but the last quantizer is cancelled. In this architecture, if a multi-bit quantizer is used in any noise shaping loop except the first loop, then the nonlinearities of the multi-bit DAC will not show up at the input to the sigma delta ADC. Instead the input referred DAC nonlinearities will be shaped by the noise shaping loops that pre- cede the multi-bit quantizer. Thus, the sigma-delta ADC can show significant improvement in SNDR while not having very strict linearity requirements on the internal multibit DACs.

  The problem with the multibit MASH architec- ture described above is that the multibit noise shap- ing loop requires an op amp, multi-bit ADC and multi-bit DAC which are difftcult to design and...