Browse Prior Art Database

ACCURATE LOGIC TIMING SIMULATIONS BY PROPAGATING SIGNAL DELAYS AND TRANSITION TIMES

IP.com Disclosure Number: IPCOM000007782D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-23
Document File: 3 page(s) / 177K

Publishing Venue

Motorola

Related People

Syed A. Aftab: AUTHOR [+3]

Abstract

Accurate simulation of delays in logic circuits is normally performed using gate-level context descrip- tions. The delays through each gate is individually analyzed, and propagated from one gate to the next in the signal path. Typical logic simulators can only propagate the logic states (unit delays). However, the delays are ohen strongly dependent on the slope of the input waveform and the output capacitance (loading). For a given set ofprocess (P), voltage (V), temperature (T) and matching (M) conditions and geometry, The output capacitances (in an average sense) are usually extracted in a pre-simulation step. How- ever, input transition time cannot be accurately esti- mated prior to simulation, since it dynamically changes from one gate to the next in the signal path. The delays are thus dependent on the location of the gate in the signal path. This report presents a process to perform accurate delay simulations using standard logic simulators, taking into account the output capacitance loading and the dynamically changing input transition times. Furthermore, sta- tistically accurate delay models can be implemented by taking into account the PvT,M conditions, as well.

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Technical Developments

ACCURATE LOGIC TIMING SIMULATIONS BY PROPAGATING SIGNAL DELAYS AND TRANSITION TIMES

by Syed A. Aftab, Mark FL Rencher and Brad Gunter

  Accurate simulation of delays in logic circuits is normally performed using gate-level context descrip- tions. The delays through each gate is individually analyzed, and propagated from one gate to the next in the signal path. Typical logic simulators can only propagate the logic states (unit delays). However, the delays are ohen strongly dependent on the slope of the input waveform and the output capacitance (loading). For a given set ofprocess (P), voltage (V), temperature (T) and matching (M) conditions and geometry,

  The output capacitances (in an average sense) are usually extracted in a pre-simulation step. How- ever, input transition time cannot be accurately esti- mated prior to simulation, since it dynamically changes from one gate to the next in the signal path. The delays are thus dependent on the location of the gate in the signal path. This report presents a process to perform accurate delay simulations using standard logic simulators, taking into account the output capacitance loading and the dynamically changing input transition times. Furthermore, sta- tistically accurate delay models can be implemented by taking into account the PvT,M conditions, as well.

INTRODUCTION

delay = f (Input transition time, Output Loading)

Current Practice:

Identical Input Transition Times at each gate; delay = 8 * delay-h1 (invt) + 7 * delay-lh (invl)

-1. bslcae ~Typtcntcase ..:, womtcase ,6- 3V bianos75 data


-s
r:
%

*cJ-

Fig. 1 Accuracy ofdelay models with and without input slope effects for 3V bicmos75 process

a Moloml4 he. 19% 89 August 1996

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0 M

MOVVROLA Technical Developments

Alternatively, the characterization may be performed using direct silicon measurements.
3) Extracting the output loading conditions (fan-out) as a function ofgeometry in a pre-simulation step. For statistical analysis, PyT,M are also included in the list of independent parameters.
4) Dynamically i.e., during simulation, encoding the output logic signal state and slope information from the logic performance functions as an ana- log event (a double precision number) instead of a digital event.
5) Decoding the input slope information from the corresponding encoded analog input event.
6) Propagating the delays and its variations through signal paths using analog events within an event driven simulator.

  Accurate characterization of delays and output slopes at various levels is an important aspect of the process presented here. The accuracy of the delay simulations is crucially dependent on the accuracy ofthe delay models.

  Another important factor in obtaining high accu- racy simulations is the extraction of the output fanout loading. An accurate physical-based capacitance model (in an average sense) as hmctions of geome- try (and EV,T,M for s...