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PARTITIONING AND ADDRESSING SCAN CHAINS

IP.com Disclosure Number: IPCOM000007792D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-24
Document File: 3 page(s) / 157K

Publishing Venue

Motorola

Related People

Charles Kirtland: AUTHOR

Abstract

As IC's grow more dense in transistor count the time it takes to test those It's also grows. Most designers are looking for ways to reduce the test time while improving the test coverage. One solution is to use a lull scan approach where each and every latch or flip flop is on a serial scan chain that can be written and then read back out. In order to reduce the time required to test the chips this long serial scan chain is usually broken up into many smaller chains and presented to the IC testers in a parallel fashion so that multiple vectors can be presented with every clock. The problem with this approach is that scannable latches and flip flops are larger than their non-scan cousins. This increases the sili- con area used to implement the complete designs. If the area is bigger, then the cost per die is also increased which is something that the designers would like to avoid. Another way to justify the scan logic might be if it could be reused so that another function might also use the chains. This allows the increased area to be amortized over another feature that might add value for the user as opposed to the manufacturer. In the case ofmicroprocessors the extra feature might be On Chip Emulation (OnCE). OnCE is an aid to software engineers debugging their code. It allows them to stop the processor and examine the state of the machine and then change it if required. The entire programmers model must be available for examination and adjustment. The focus ofthis paper is the reuse of the scan chains for OnCE.

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MOFOROLA Technical Developments

PARTITIONING AND ADDRESSING SCAN CHAINS

by Charles Kirtland

  As IC's grow more dense in transistor count the time it takes to test those It's also grows. Most designers are looking for ways to reduce the test time while improving the test coverage. One solution is to use a lull scan approach where each and every latch or flip flop is on a serial scan chain that can be written and then read back out. In order to reduce the time required to test the chips this long serial scan chain is usually broken up into many smaller chains and presented to the IC testers in a parallel fashion so that multiple vectors can be presented with every clock. The problem with this approach is that scannable latches and flip flops are larger than their non-scan cousins. This increases the sili- con area used to implement the complete designs. If the area is bigger, then the cost per die is also increased which is something that the designers would like to avoid. Another way to justify the scan logic might be if it could be reused so that another function might also use the chains. This allows the increased area to be amortized over another feature that might add value for the user as opposed to the manufacturer. In the case ofmicroprocessors the extra feature might be On Chip Emulation (OnCE). OnCE is an aid to software engineers debugging their code. It allows them to stop the processor and examine the state of the machine and then change it if required. The entire programmers model must be available for examination and adjustment. The focus ofthis paper is the reuse of the scan chains for OnCE.

  In full scan designs all the latch and flip flops are on one of the many scan chains, if the portion of the microprocessor that relates to the programmers model such as the instruction register, program coun- ter and address bus are gathered together and place on a single scan chain then the job of changing the flow of program is made easier. The majority of the

chip is not required to change the flow of the pro- gram but must be lefi static to preserve the sanity of the chip. An example might be the logic used to control the nature of the fetch, decode and execute of instructions within the instruction pipe. OnCE allows the user to change the instructions-not the way they perform. As a result, how the elements on the scan chains are allocated and well as how a sin- gle chain can be addressed is the real topic exam- ined here. Multiple scan chains require multiple clock regenerators which is not a prroblem since most designs place identical copies of the same regenera- tor for loading and skew purposes. The difference here is that all the regenerators that drive logic con- tained on a given scan chain have same control but different from all the other chains. That control is derived from a piece of logic called a router. The routers are placed within a fimctional block and serve to control the regenerators and direct the flow of d...