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POWER ANALYSIS OF CMOS CIRCUITS USING SWITCH-LEVEL SIMULATION

IP.com Disclosure Number: IPCOM000007794D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-24
Document File: 9 page(s) / 515K

Publishing Venue

Motorola

Related People

S. Gavrilov: AUTHOR [+6]

Abstract

The subject of low power IC design is ofparticu- lar interest over the last two or three years [I]. Static CMOS circuits are very suitable for this purpose since they do not consume power in the stationary state. The goal of the research reported in this paper was to develop a fast and accurate method for power estimation of CMOS circuits which can be used in algorithms that optimize CMOS designs.

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M-LA Technical Developments

POWER ANALYSIS OF CMOS CIRCUITS USING SWITCH-LEVEL SIMULATION

by S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. Jones and G. Vijayan

1. INTRODUCTION

  The subject of low power IC design is ofparticu- lar interest over the last two or three years [I]. Static CMOS circuits are very suitable for this purpose since they do not consume power in the stationary state. The goal of the research reported in this paper was to develop a fast and accurate method for power estimation of CMOS circuits which can be used in algorithms that optimize CMOS designs.

  There are two broad approaches for power loss calculation in CMOS circuits. In the first approach, the specific times of input switchings are not con- sidered. Only average switching Frequencies of inputs are taken into account. Also, the power loss is esti- mated based only on switchings ofgate outputs and the switchings of internal nodes within a gate are not taken into account. This approach is used for timing correction in logic synthesis [2] and power optimization during technology mapping of CMOS circuits [3,4]. This approach can be described as static power estimation.

  The second approach takes into account the spe- cific times of the input switchings. In this case the switchings of all internal nodes are also considered, and therefore the estimate of power loss is much more accurate than the first approach. We consider this dynamic approach in this paper.

  The dynamic approach uses simulation of input vectors at some level. To select a proper method of electrical simulation, a number of simulation tech- niques were considered. Certainly, a detailed circuit simulation (such as SPICE) is too time consuming. Various simplified modifications of detailed circuit simulation were examined. For example, the ELOGIC algorithm [5] was considered, and a proto- type power estimator was implemented. However,

these methods demonstrated insufficient productiv- ity for use in circuit optimization. Gate level circuit simulation was found to be insufficiently accurate since it does not monitor the switchings of internal circuit nodes.

  Switch-level simulation [6,7] was chosen as the method for power loss calculation to be used as a power estimator within optimization algorithms. The standard switch level simulation algorithms are pri- marily intended for logic simulation or timing veri- fication. Exact values of potential for all circuit nodes are not calculated. Therefore, to calculate power loss, the standard method should be modified.

It should be noted that power estimation using switch level simulation has already been developed
[8]. In this prior case a commercially available sim- ulator was used. However, the main drawback of this approach is that exact values of node potentials were not calculated, as only the logical (O,l} set was used for simulation. Furthermore, short-circuit power was not estimated.

  The importance of using the exact values of node potentials for...