Browse Prior Art Database

Method for BGA package design

IP.com Disclosure Number: IPCOM000007808D
Publication Date: 2002-Apr-24

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for ball grid array (BGA) package design. Benefits include improved thermal performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 49% of the total text.

Method for BGA package design

Disclosed is a method for ball grid array (BGA) package design. Benefits include improved thermal performance.

Background

              The conventional BGA package design is square (see Figure 1). Some space is wasted at the package edge.

              High speed signaling has become a requirement for all communications chips. To be competitive, the cost of the product should be minimal. The major cost component of the conventional product includes the package in which the die is enclosed. Package technologies range from low-cost low-bandwidth packages (less than $1 each) to high-cost high-bandwidth packages (more than $100 each). Package selection depends on performance requirements. Design optimization of cheaper package technologies can extend the bandwidth of the package, enabling their use for high-speed applications.

              Wire bond packages are a staple of packaging technology. The wire bonds are used to transfer signals off the die, onto the package substrate, and out to the system board. This transfer is achieved by the help of the solder balls on the package. Design time, electrical signal integrity, and route density depend on the route feasibility from the wire bonds to the solder balls.

              High-power devices have special thermal requirements. These devices rely on dissipating heat from the die into the package and out to the ambient environment with the help of solder balls on the package. Thermal resistance is minimized when the silicon substrate is directly connected to the system board through an array of solder balls placed directly underneath the die.

      Wire-bond fan out naturally orients itself in a radial fashion. This fan out conflicts with the square ball-grid pattern provided in standard BGA packages, resulting in the following side effects:

§         Increased design cycle times

§         Decreased routing density on package and board.

§         Unwanted signal integrity effects like skew mismatches, bends, and random angle routes, which implies increased design cycle time to validate the design

§         Lower ball count for a given area

Description

              The disclosed method includes a ball grid configuration pattern that addresses the side effects from the conflict between the square ball-grid pattern and wire-bond fan out.

              The radial shape is centered and uses space more efficiently than the conventional square design (see Figure 2). For example, assume a ball pad size of 600 µm, minimum radial pitch and ball-to-ball pitch of 1 mm, and ball-to-edge spacing of 200 µm. A 23-mm by 23-mm array can have a ball count of 484 with a square arrangement and 490 with a radial arrangement. A 34-mm by 34-mm array can have a ball count of 1156 with a square arrangement and 1163 with a radial arrangement. Package design rules (trace, space, and via) are the same for conventional BGA. Selecting the optimum ball count required and developing a custom solution can further optimize package design (see Figure 3).

              A 23-mm by 23-mm package demonstrates route feasibility (see Figure...