Browse Prior Art Database

SECOND ORDER CMOS FILTER

IP.com Disclosure Number: IPCOM000007818D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-25
Document File: 2 page(s) / 64K

Publishing Venue

Motorola

Related People

David Susak: AUTHOR

Abstract

The proposed circuit is shown in Figure 1. The intent of this circuit is to take a digital logic signal and filter it such that it has a controlled slew rate and no sharp comers.

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Technical Developments

SECOND ORDER CMOS FILTER

by David Susak

  The proposed circuit is shown in Figure 1. The intent of this circuit is to take a digital logic signal and filter it such that it has a controlled slew rate and no sharp comers.

  Node A receives the input digital logic signal. MOS transistors M4 and M5 act as a current switch. When Node A is high the current in M7 pulls Node B to a lower voltage. When Node A is low the cur-

rent in M2 pulls Node A to a higher voltage.

  I1 is a reference current which biases Ml and M6. M2 and M7 then mirrors reference current Il. The positive slew rate at Node C is defined by the drain current of M7 and Cl: The negative slew rate at Node C is defined by the drain current of M2 and Cl.

The rounding of the comers of the waveform at Node C are caused by the change in current in M2

and M7. At Point 1 of Waveform C Node A is low, transistors M2 and M7 are in the linear region of operation. This means that transistors M2 and M7 have zero drain current. When Node A switches high transistor M2 stays in the linear region but transis- tor M7 begins to conduct current and eventually enters the saturation region. This transition creates a rounded comer at Point 1 of Waveform C. When transistor M7 enters the saturation region its drain current is constant and provides a constant slew rate. As the voltage at Node B approaches Vss transistor M7 begins to go back into the linear region. This means that the drain current oftransistor M7...