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Built In Self Test Improvement for Charge Redistribution Analog to Digital Converter

IP.com Disclosure Number: IPCOM000007828D
Original Publication Date: 2002-Apr-25
Included in the Prior Art Database: 2002-Apr-25
Document File: 4 page(s) / 44K

Publishing Venue

Motorola

Related People

Al Heiden: AUTHOR

Abstract

A method is described to improve the efficiency of test for the charge redistribution analog to digital converter (ADC). This type of converter was first described in James L. McCreary and Paul R. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques," IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, at pages 371-379 and also U.S. Pat. No. 4,129,863

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Built In Self Test Improvement for Charge Redistribution Analog to Digital Converter

Al Heiden

Abstract

A method is described to improve the efficiency of test for the charge redistribution analog to digital converter (ADC). This type of converter was first described in James L. McCreary and Paul R. Gray, "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques," IEEE Journal of Solid State Circuits, Vol. SC-10, No. 6, December 1975, at pages 371-379 and also U.S. Pat. No. 4,129,863.

The converter uses a duplicate but inactive capacitor array to match the active array. Then during initialization, the reference voltage (Vcm) can be established. The inactive array is termed the “reference array”.

In this test improvement the reference array is connected just as the active array. During test, the arrays must be found to closely match during the conversion sequence. If a close match is not observed due to a processing defect, the device can then be rejected during production testing. Testing in this way allows for a dramatic improvement in test execution time.

Implementation Detail

The improvement is implemented by the following means:

1-     The approximation logic is modified to allow for independent control apart from the control provided by the sequencer of the ½ LSB capacitor in the array.

2-     A duplicate of the modified successive approximation logic block is then connected to the reference capacitor array. The comparator output signal is connected to both approximation logic stages. The intent is to cause both stages to behave identically during a conversion.

3-     Reference to the figure below shows a converter after the described modification. A test control bit is required such that the reference array will be inactive during normal conversions. Assertion of the “TST” signal will cause the converter to enter the test mode and it will not provide a normal output conversion code.

Detail of Testing

Testing of the device can be accomplished by the following means:

1-     Before conversion, a voltage representing the maximum allowed conversion input voltage is applied at Vin.

2-     Also before conversion, the ½ LSB capacitor of the reference array is connected to ground using th...