Browse Prior Art Database

SMALL-AREA, LOW-POWER INSTRUCTION DECODER

IP.com Disclosure Number: IPCOM000007832D
Original Publication Date: 1996-Aug-01
Included in the Prior Art Database: 2002-Apr-29
Document File: 2 page(s) / 104K

Publishing Venue

Motorola

Related People

Chen Goldenberg: AUTHOR [+3]

Abstract

Powerful data processing chips may have large instruction sets containing as many as 500 instruc- tions. In order to support such a large instruction set, a chip requires a large decoder to handle these instructions. However, a large decoder increases the power requirements of the chip and consumes valu- able space on the chip.

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m M-LA Technical Developments

SMALL-AREA, LOW-POWER INSTRUCTION DECODER

by Chen Goldenberg, Natan Baron and Zvika Rosenshein

  Powerful data processing chips may have large instruction sets containing as many as 500 instruc- tions. In order to support such a large instruction set, a chip requires a large decoder to handle these instructions. However, a large decoder increases the power requirements of the chip and consumes valu- able space on the chip.

  During normal processing, only a small set of instructions are actually used for a large part of the running time. In a chip such as the 56301 (ONYX) digital signal processor approximately 80% of the running time is dedicated to decoding only eight instructions.

  Previously, common instructions such as DALU operations in parallel with data moves have been decoded using a single large decoder logic that also handles all other instructions. The power consumed by this large decoder logic is considerable, even for instructions requiring relatively small logical opera- tions to be carried out.

  It is therefore desirable to optimize the power and area requirements of the decoder, whilst maintaining good operating speed. This has been achieved by splitting the decoder into two parts: a small decoder containing logic for handling the few, most common instructions and a large decoder for processing the rest ofthe instruction set.

instruction:' the clock generators in the large decoder are enabled and the instruction is sent to the large decoder for processing.

  If, on the other hand, any of the four MSB do not equal zero, then the predecoder recognizes the instruction as a "small decoder instruction:' disa- bles the clock generators of the large decoder, and sends the instruction to the small decoder for processing. By disabling the clock generators of the large decoder in this way, all of the inputs of the large decoder remain unchanged during the processing of a small decoder instruction. Since the inputs are unchanged, none of the many gates in the large decoder logic change state during this period; hence power i...