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V2HWE: A RAPID PROTOTYPE TRANSLATOR FROM VERILOG-XL LANGUAGE TO HARDARE EMULATION

IP.com Disclosure Number: IPCOM000007846D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-Apr-29
Document File: 5 page(s) / 186K

Publishing Venue

Motorola

Related People

Jeff Freeman: AUTHOR

Abstract

Hardware emulation is used by Motorola design teams to increase their confidence in 100% hmc- tional silicon and to decrease the design cycle time.

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M-ROLA Technical Developments

8

V2HWE: A RAPID PROTOTYPE TRANSLATOR FROM VERILOG-XL LANGUAGE TO HARDARE EMULATION

by Jeff Freeman

INTRODUCTION

  Hardware emulation is used by Motorola design teams to increase their confidence in 100% hmc- tional silicon and to decrease the design cycle time.

  Verilog-XL to hardware emulation (V2HWE) is a software program that translates and maps a Verilog-XL language to a EDIF 2.00 netlist which can be read by hardware emulation products. It includes a set of scripts that use Motorola SSDT's verilog2edif program to quickly map a design to a generic library of 14 elements. The library is then translated to a netlist for hardware emulation.

  Normally, a design must be optimized for speed and area through the synthesis process before it is ready for hardware emulation. This can take several days for large designs. For some design flows in other companies, the design must also go through pre-

The Old Process:

  A Verilog-XL. synthesizeable subset is read into a synthesis tool such as Synopsys. This is called a behavioral model ofthe design. See Figure 1.

silicon layout before it is ready for the hardware emulator. The new hardware emulation design flow proposed by this paper does not have this restriction.

  This paper proposes a method for generating hardware emulation netlist from the functional description of a design. This is significant because the designer can run millions of cycles per second on a hardware emulator compared to under 10 cycles per second for a Verilog-XL simulation (based on 68060 experience with Quickturn Systems which is a hardware emulator vendor).

DESCRIPTION

Behavior

HDL Model

1

Optimization (Synopsys)

(may take days)

(One-time, may take months
to generate) 1

Gate-leVFJl Stdcell mapped netlist

Stdcell mapped

A EDIF

. .

&$2y~g~+,

Fig. 1 Old and New Hardware Emulation Process

0 Motorola. 1°C. 1996

12

November 1996

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MOTOROLA Technical Developments

  Relaxed constraints are applied since the primary design goal is to produce a minimum area standard cell mapped gate-level netlist. Note that the final netlist is really an abstraction from what standard cells are used on the final silicon design. The stand- ard cells of the gate-level netlist are actually built up of the primitives of the emulation software and hardware library. The new process described below is just a further abstraction from the silicon, but is functionally equivalent.

The New Process:

  As in the old process, the new process still has the Verilog-XL synthesizeable subset model as the input.

  The program, V2HWE maps the Verilog-XL model to a generic set offourteen primitive cells on the order of minutes. No logic optimization is done

(hence the speed), so it is apparent that this new process is better for small designs whose size fits easily into a hardware emulation board. Before an EDIF netlist can be sent to the emulation sollware, a mapping from the g...