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REGISTER-TRANSFER LEVEL (RTL) DELAY MODELING AND A METHOD FOR RTL DELAY CALCULATION

IP.com Disclosure Number: IPCOM000007851D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-Apr-29
Document File: 6 page(s) / 227K

Publishing Venue

Motorola

Related People

Kayhan Kucukcakar: AUTHOR

Abstract

As the complexity of designs increase and higher- level tools become available for digital design, delay calculation continues to be a challenging area.

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Page 1 of 6

0 M MolylRoLA

Technical Developments

REGISTER-TRANSFER LEVEL (RTL) DELAY MODELING AND A METHOD FOR RTL DELAY CALCULATION

by Kayhan Kucukcakar

tiple bits per port. An example is shown in Figure
1. Block A in Figure 1 has n input ports where each input port Ij has the bitwidth of ibwj and has m output ports where each output port 0. has a bitwidth of obwj. Block A can be an adder, A L U, multiplier, RAM, ROM, multiplexer, register, shifier, crossbar switch, bus or similar. The delays (generally the lowest maximum delays) between all ports should be modeled and characterized.

A general block representation for logic, data- path or memory block.


1.0 INTRODUCTION

  As the complexity of designs increase and higher- level tools become available for digital design, delay calculation continues to be a challenging area.

  As the complexity of designs increase, delay cal- culation methods which were previously satisfactory can not handle new designs. A similar problem has been seen in the past where the speed of circuit simulation became a significant bottleneck on large logic blocks. Then, it becomes impossible to run circuit simulation on complete designs even though there was no other delay calculation methods with similar accuracy. Most designers had to switch to logic-level delay modeling for the speed up at some of the accuracy.

  The second generation of this problem is starting to happen. Even logic level delay modeling is becom- ing too slow to run on large designs. Wtth the intro- duction of HTL and higher-level tools there is a urgent need for accurate, efftcient, and fast RTL delay cal- culation techniques. Especially, designs containing data-path components and memories cause signifi- cant run-time explosion for current delay calcula- tion methods.

  This paper describes an RTL delay modeling for digital design and a technique for performing delay calculations. Both the delay model and the delay calculation technique are intended for static delay calculation, RTL and higher-level synthesis, and simulation.


2.0 PROBLEM DEFINITION

The general problem is as follows. Digital design netlists contain blocks with multiple ports and mul-

Fig. 1

  RTL delay calculation is aimed to find combina- tional delay paths between any points in a netlist. Figure 2 shows an example path from point S to point D in the netlist. RTL delay calculators should be able to calculate this path accurately and fast. It should be noted that when points Sand Dare multi- bit nets, the delay calculations need to get a path for each bit ofthe nets.

B Motorolr. Inc. ,996 27 November1996

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Page 2 of 6

Technical Developments

Delay Calculation The requirements on the delay calculation are

l

efficiency in storage component propagation delays

l

accuracy

run-time speed

uniform handling oflogic and large blocks

capability to support back annotation

compatibility with existing wire delay models

easy modeling capabilities for e...