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A Low Voltage Side Fired Transient Voltage Suppressor Construction Method.

IP.com Disclosure Number: IPCOM000007854D
Publication Date: 2002-Apr-29
Document File: 11 page(s) / 1M

Publishing Venue

The IP.com Prior Art Database

Abstract

Many current and emerging electronic applications require transient voltage protection on the low value range (for example 5V to 80V breakover range) along with low capacitance values for lower signal distortion on communication circuits. Prior art has used surface breakdown or offset buried region design concepts, however, they are more complex to build and manufacture due to problems like leakage. Thus, there has been a need for a bi-directional or unidirectional TVS device design having low BV values, good surge capability and medium to high IH (holding current) levels with reasonable wafer manufacture-ability while fully compliant with the most demanding customer specs concerning capacitance and surge needs.

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A Low Voltage Side Fired Transient Voltage Suppressor Construction Method.

Many current and emerging electronic applications require transient voltage protection on the low value range (for example 5V to 80V breakover range) along with low capacitance values for lower signal distortion on communication circuits.  Prior art has used surface breakdown or offset buried region design concepts, however, they are more complex to build and manufacture due to problems like leakage.

Thus, there has been a need for a bi-directional or unidirectional TVS device design having  low BV values, good surge capability and medium to high IH (holding current) levels with reasonable wafer manufacture-ability while fully compliant with the most demanding customer specs concerning capacitance and surge needs. 

A localized Zener region  is created using active (IH defining) diffused layers on top of which or aside of which a shallow  groove is made and passivated so that surface leakage is reduced. Alternatively, the Zener region can be established at an enhancement diffused layer which might or might not be active. The combination of the two layers (active and enhancement) can also be used for this purpose.

This creates a bi-directional or unidirectional semiconductor transient voltage suppressor having on its active gate or enhancement gate diffused layers a breakdown defining PN junction created by a diffused layer of the same conductivity type as that of the bulk and as that of  the cathode layer(s). In addition, a passivated parallel or vertical shallow groove is engraved selectively on the breakdown defining PN junction; this is aimed to reduce surface leakage problems.

Cross Section Schematics of an N-Type Side Fired TVS With Low VZ. Mesa Option 1, Case 1.

 
 

Case 1 Zener on Inside Heavily Doped Active Layer 

Lightly doped, junction capacitance defining P-type layers 2 and 3 are selectively deep diffused into a very lightly doped, N-type wafer 1 (for example, 10-100 Ohm-cm resistivity) . A similar or higher dopant dose is used on P-type layers 4 and 5 which are selectively diffused inside layers 2 and 3; this sequential diffusion is profiled so that both combined define the device Vz and IH level on this configuration. Heavily doped N-type regions 6 y 7 making contact to the N- bulk 1 and forming a PN junction with layers 2 and 4 on one side and to layers 3 and 5 on the opposite side are then created either by a selective dedicated diffusion or preferentially during the selective cathode diffusion (layers 8 and 9). In order to avoid surface breakdown limitations (poor leakage control), shallow grooves (deep 2-4 micron, mesa-like) 10, 11 are selectively etched and passivated. Sites marked with a * is where the junction breakdown mechanism takes place. Metal contacts 12 and 13 are selectively deposited by any conventional process.

For the P-type TVS case, the conductivity type on all layers is reversed.

Case 2 Zener on Inside Lightly Doped Active Layer

Lightly doped, ju...