Browse Prior Art Database

GAP LOGIC FOR GLOBAL SYNCHRONIZATION

IP.com Disclosure Number: IPCOM000007861D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-Apr-30
Document File: 2 page(s) / 92K

Publishing Venue

Motorola

Related People

James McDonald: AUTHOR [+2]

Abstract

The gap logic described below is used in PLL based systems where in addition to the reference and feedback signals, referred to as clocks, being aligned by the PLL, there is a second set of signals, referred to as syncs, which must be aligned. The relationship between the syncs and the clocks must be maintained during alignment of the syncs. The alignment of the syncs while maintaining a strict relationship with the clocks is accomplished with the gap logic.

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Technical Developments

GAP LOGIC FOR GLOBAL SYNCHRONIZATION

by James McDonald and Nandini Srinivaeen

PURPOSE OF GAP LOGIC:

turn the pulse swallowing off, thus disabling the gap logic, and how to implement the pulse swallowing algorithm.

  The gap logic described below is used in PLL based systems where in addition to the reference and feedback signals, referred to as clocks, being aligned by the PLL, there is a second set of signals, referred to as syncs, which must be aligned. The relationship between the syncs and the clocks must be maintained during alignment of the syncs. The alignment of the syncs while maintaining a strict relationship with the clocks is accomplished with the gap logic.

GAPPING ALGORlTHM:

CONCEPTUAL DESCRIPTION;

  With the input clock phased-locked to the out- put clock and the input sync aligned with the out- put sync the system is in an up and locked condi- tion. As long as the syncs remain aligned, the PLL works to frequency and phase lock the clocks as in any standard PLL based system. However, if the syncs move out ofalignment, the gap logic works to realign the input sync with the output sync. This realignment is accomplished by swallowing pulses of either the reference or feedback clock, depending on whether the output sync needs to speed up or slow down relative to the input sync. Once the syncs are realigned, the "pulse swallowing" is turned off and the PLL operates in standard fashion to align the clocks.

  There are several issues which must be addressed for the successful operation of the gap logic. These issues include determining when the syncs are...