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Browse Prior Art Database

ENHANCED DRAIN FORMATION FOR 1.5T FLASH

IP.com Disclosure Number: IPCOM000007862D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-Apr-30
Document File: 4 page(s) / 175K

Publishing Venue

Motorola

Related People

Danny P. Shum: AUTHOR [+3]

Abstract

A new drain region process to control erased V, distribution by moving drain junction implants after the ON0 formation has been proposed for a 16-bit microcontroller with embedded flash EEPROM memory. The new integration reduces drain implant mask alignment sensitivity and improves the proc- ess to be forgiving and manufacturable. This improve- ment is believed to carry the current 0.65 pm flash technology into next generation of 0.55 ,um regime and beyond.

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Page 1 of 4

M-LA Technical Developments

ENHANCED DRAIN FORMATION FOR 1.5T FLASH by Danny F? Shum, Ko-Min Chang and William J. Taylor

ABSTFIACT

  A new drain region process to control erased V, distribution by moving drain junction implants after the ON0 formation has been proposed for a 16-bit microcontroller with embedded flash EEPROM memory. The new integration reduces drain implant mask alignment sensitivity and improves the proc- ess to be forgiving and manufacturable. This improve- ment is believed to carry the current 0.65 pm flash technology into next generation of 0.55 ,um regime and beyond.

INlRODUCTlON

  In high density NVM applications, the first con- cern is the over-erasure problem of the memory array as with other conventional lT-cell approaches. This problem was driven by the process variation of the thin tunnel oxide formation for erase. An alterna- tive approach to this problem is the use of an enhancement transistor in series with the cell. This is the so-called split-gate structure whose V, is the target erased V, ofthe cell. Thus the split-gate struc- ture eliminates the over-erasure problem completely. For high performance applications, the drain engi- neering is tailored by an abrupt junction as well as

short channel length. Hot carrier injection (HCI) was chosen over FN programming to achieve fast program time. Low programming voltage is also needed to reduce program disturb problem. Thus, the drain engineering is tailored by extension implant of arsenic (As) and DSA implant of boron (B) to enhance the hot-electron generation, as shown in FQure 1. In this approach, a high dose boron implant is performed only on the drain side prior to ON0 formation [l-2]. The boron implant is high energy so that it penetrates through the poly gate while the arsenic implant is selcaligned to the gate edge. The boron coverage of the drain is always very good which leads to an abrupt drain junction under the gate edge to facilitate fast programming speed. The drawback is making the alignment critical at this level. The problem lies on the high heat from the post-annealing step during the formation of the ON0 interpoly die- lectric. Misalignment of the mask could cause some of the boron out-diffuse to the split gate side and effectively raise its V,. Another concern from the alignment is the asymmetrical cell behaviour due to different orientation, as shown in Figure 2. The ori- entation dependence causes odd and even word line failure. Overall, alignment sensitivity of this level is key to the shrinkability ofthe cell.

Split Floating Gate Gate

Fig. 1 Cell cross-section along the source/drain junction.

D Mmmla, 1°C. 1996 56 November 1996

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Technical Developments

Fig. 2 Schematic ofa 4-bit cell array.

  In this work we propose a new integration scheme to reduce lateral diffusion from the boron as well as minimize silicon damage from implantation. No new or complex processes are a...