Browse Prior Art Database

ROBUST METHODOLOGY AND SOFTWARE FOR ALGORITHMIC TESTING OF MEMORY ARRAYS

IP.com Disclosure Number: IPCOM000007876D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-May-01
Document File: 2 page(s) / 76K

Publishing Venue

Motorola

Related People

Anup S. Tirumala: AUTHOR [+3]

Abstract

Embedded memories need to be tested for defects and their ability to operate reliably at the target speed. Adhoc testing can be'used for this purpose.

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ROBUST METHODOLOGY AND SOFIWARE FOR ALGORITHMIC TESTING OF MEMORY ARRAYS

by Anup S. Tirumala, Clark G. Shepard and Daniel T. Marquette DEFINITION OF THE PROBLEM

  Embedded memories need to be tested for defects and their ability to operate reliably at the target speed. Adhoc testing can be'used for this purpose.

  Some hardware testers have the capability to gen- erate algorithmic test sequences to be applied dur- ing adhoc test mode. Because these tests are run on the hardware tester during production, they have historically been applied for the first time post-silicon. Pre-silicon tests are usually developed and verified by a different person. Many problems arise due to multiple verification environments and multiple peo- ple generating the test sequences.

  The methodology and software tool presented attempts to apply the tests derived from the hard- ware tester pre-silicon. By unifying the simulation and hardware environments me same tools and tech- niques can also be used to translate test sequences

between various hardware testers. DESCRIPTION OF THE METHODOLOGY AND SOFIWARE

  The flow is shown in Figure 1. The simulation model consists of the processor and the adhoc testcard. These are both typically written in a high- level modeling language. As the design progresses, the processor can be replaced with a gate-level netlist. To test for operation at the target frequency, the gate- level netlist can have capacitances back-annotated to it and the simula...