Browse Prior Art Database

HIGH FREQUENCY CMOS BUFFER AMPLIFIER

IP.com Disclosure Number: IPCOM000007880D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-May-01
Document File: 3 page(s) / 123K

Publishing Venue

Motorola

Related People

Scott Humphreys: AUTHOR

Abstract

It is ofien desirable to use CMOS counters and prescalers to measure the frequency of an analog (sinusoidal) signal, or for using such a signal as a clock for CMOS logic circuits. CMOS logic requires signal swings of at least a few hundred millivolts about the half-supply point. Frequently, a discrete transistor and LC tank circuit AC coupled to an input, biased at half-supply, provide amplification of low amplitude, high frequency signals. Trimming requirements ofthe LC tank lead to manufacturability difficulties and cost increases, and large signals in an LC tank create RF interference. A preferable approach is to implement a fully integrated broad- band amplifier.

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Technical Developments

HIGH FREQUENCY CMOS BUFFER AMPLIFIER

by Scott Humphreys

adds the parasitic capacitance of integrated capaci- tor structures (typically 10 to 30% ofthe capacitance value) to the signal path. Both options decrease the gain available at a given current drain, and there- fore, the efficiency of the amplifier.

BACKGROUND:

SOLUTION:

  It is ofien desirable to use CMOS counters and prescalers to measure the frequency of an analog (sinusoidal) signal, or for using such a signal as a clock for CMOS logic circuits. CMOS logic requires signal swings of at least a few hundred millivolts about the half-supply point. Frequently, a discrete transistor and LC tank circuit AC coupled to an input, biased at half-supply, provide amplification of low amplitude, high frequency signals. Trimming requirements ofthe LC tank lead to manufacturability difficulties and cost increases, and large signals in an LC tank create RF interference. A preferable approach is to implement a fully integrated broad- band amplifier.

  Typical CMOS buffering techniques provide a starting point. The most common buffering tech- nique employs a chain of inverters where each suc- cessive inverter is scaled up in drive capability, Plac- ing a feedback resistor from the output to the input of each stage biases the circuit by forcing the inverter inputs and outputs to stabilize at, or near, the switching point ofthe inverters (see Figure 1).

  Unfortunately, simple scaling of the transistor sizes of successive stages does not provide adequate matching of the DC characteristics of the amplifier stages over process, temperature, and supply varia- tions. These variations cause one stage to bias up at a slightly different point than the next, and the out- put signal of the one stage does not always swing around the switch point of the next stage. In one case, the output of the first stage is centered below the switch point of the second stage, causing the second stage output to swing about a point above the switch point ofthe third stage. The result is that the third stage output remains near ground. Typical solutions to this problem are to lower the value of the feedback resistors or to add series coupling capac- itors between each stage. However, the first method employs increased feedback, and the second method

  The fundamental problem is that the DC char- acteristics ofthe devices, and...