Browse Prior Art Database

INTEGRATED STACKED GATE OXIDE AND INTERPOLY OXIDE

IP.com Disclosure Number: IPCOM000007891D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-May-02
Document File: 2 page(s) / 110K

Publishing Venue

Motorola

Related People

Craig Cavins: AUTHOR [+5]

Abstract

For microcontrollers with embedded EEPROM, burn-in cost can be as high as $0.25 per part. The dominant burn-in failure mode has been the EEPROM select gate failures. A process for 1.2 pm design rules uses a 35OA thermal oxide for the select gate. It is desirable to make this select gate dielec- tric more robust in order to reduce or eliminate the burn-in failures and thereby eliminate the need for a costly burn-in.

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Technical Developments

INTEGRATED STACKED GATE OXIDE AND INTERPOLY OXIDE

by Craig Cavins, Ko-Min Chang, Craig Swift, Hsing-Huang Tseng and Wayne Paulson

PURPOSE:

  For microcontrollers with embedded EEPROM, burn-in cost can be as high as $0.25 per part. The dominant burn-in failure mode has been the EEPROM select gate failures. A process for 1.2 pm design rules uses a 35OA thermal oxide for the select gate. It is desirable to make this select gate dielec- tric more robust in order to reduce or eliminate the burn-in failures and thereby eliminate the need for a costly burn-in.

  The integration ofthe 1.2/rm process is such that the select gate dielectric is formed concurrently with the interpoly dielectric for the EEPROM bit cell, and the logic gate dielectric is identical to the select gate dielectric. The enmeshment of these processes gives little latitude for significantly improving the quality of the select gate dielectric within the confines of a conventional approach which is to grow a thermal select gate oxide while simultaneously growing a thermal interpoly oxide.

  One prior art solution is to use an interpoly ON0 stack with the top oxide layer being a CVD layer which can also form at least part of the peripheral transistor dielectric. The disadvantage here is that for some self-aligned NVM integrations and for most non-self-aligned NVM integrations, the use of an ON0 interpoly dielectric requires an additional masking step to pattern the ONO.

oxides are well known.' The process sequence starts with a pre-ditfusion clean which cleans the single crystal silicon surface in the select gate (and logic gate) area and cleans the surface of the first poly floating gate, An initial thin thermal oxide may or may not be grown as the first layer of the stacked oxide. Then a CVD oxide is deposited. The ratio of C...