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Method for combining two VPP detection schemes

IP.com Disclosure Number: IPCOM000007899D
Publication Date: 2002-May-02
Document File: 3 page(s) / 158K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for combining two VPP detection schemes. Benefits include improved performance and improved usability.

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Method for combining two VPP detection schemes

Disclosed is a method for combining two VPP detection schemes. Benefits include improved performance and improved usability.

Background

              Conventionally, Flash memories use a high-voltage power supply of 12V to perform program and erase, because large electric fields are required to move a charge on and off of the floating gate. A 12V interface for programming and erasing Flash memories is advantageous because it provides fast performance and backward compatibility with prior products, which are key selling points.

              Although the 12V interface is maintained, not all customers use it all the time. The interface must be available for detecting when an application takes VPP, the 12V pin, high so that the memory can be put in the correct mode. Two methods are conventionally used for this detection (see Figure 1). One method detects high VPP for activating the correct algorithm. The high-VPP algorithm provides much faster programming and erase operations. This detector uses a Flash pair-based reference voltage compared against a VPP reference generated with a voltage divider and is activated only during algorithm processing.

              The other method detects high VPP for entering factory test modes. This detector is activated only when certain conditions are met that signals a user might be entering test modes. The detector uses a nonreference voltage-based scheme (see Figure 2.) The gate of device P1 is taken to VSS when the detector is enabled. Devic...