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VARIABLE DATA REPRESENTATION FOR HIGHER-SPEED PERFORMANCE AND REDUCED-POWER CONSUMPTION IN PRECHARGED CIRCUITS

IP.com Disclosure Number: IPCOM000007935D
Original Publication Date: 1996-Nov-01
Included in the Prior Art Database: 2002-May-07
Document File: 3 page(s) / 134K

Publishing Venue

Motorola

Related People

Merit Hong: AUTHOR

Abstract

Low power has always been a key objective of VLSI circuit design for portable products. It is also one of the reasons why CMOS has been a favored technology for the implementation of low-power VLSI designs. One of the most hequently used design techniques in CMOS is that of precharging. Unfortunately precharging forces circuit activity even when none is required. Thus to avoid unnecessary precharging overhead, it is proposed that the data representation be allowed to vary so that a choice can be made to minimize discharging. As an added benefit, significant speed improvements are simul- taneously obtained.

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Technical Developments

VARIABLE DATA REPRESENTATION FOR HIGHER-SPEED PERFORMANCE AND REDUCED-POWER CONSUMPTION

IN PRECHARGED CIRCUITS

by Merit Hong

INTRODUCTION

  Low power has always been a key objective of VLSI circuit design for portable products. It is also one of the reasons why CMOS has been a favored technology for the implementation of low-power VLSI designs. One of the most hequently used design techniques in CMOS is that of precharging. Unfortunately precharging forces circuit activity even when none is required. Thus to avoid unnecessary precharging overhead, it is proposed that the data representation be allowed to vary so that a choice can be made to minimize discharging. As an added benefit, significant speed improvements are simul- taneously obtained.

IDEA

  It is proposed that by allowing various choices of data representation, a data representation can be chosen so as to minimize Hamming distance to the precharged state. Furthermore, the data representa- tion can be inhomogeneous, i.e. data may be subdivided into smaller pieces, each with its own independent representation. Not only does this reduce the number of discharges during the evaluation phase, but it also reduces transistor count in the evalua- tion portion of the circuit, hence the loading capaci- tance seen by any driver of the evaluation circuitry, EXAMPLE

  There exist many applications, the simplest of which is the ROM. The standard ROM design is shown in Figure 1. The new ROM design is shown in Figure 2. In both ofthese figures, the precharged state is high, or "l?' Note that the new ROM will have fewer transistors. Consequently there will be

less gate capacitance on the word line, less source/ drain capacitance on the bit line. Since most of the power consumption in a ROM is attributable to word- line switching and bit-line discharging, typical power savings of the new ROM design is seen from Figures 1 and 2 to be 25%. Furthermore, worst case delay in a ROM is attributable to the maximum capacitance that can be attained on a word or bit line. Since this worst case capacitance is reduced by 50% (i.e. the standard ROM can have all of its data bits "0; whereas the new ROM has at most half of its data bits "O"), a 2X improvement in speed is obtained.

  In the example shown in Figure 2, one polarity bit specifies the representation of two data bits. It is also possible for one polarity bit to specify the rep- resentation of an arbitrary number of bits, but power savings decrease slightly as the nu...