Browse Prior Art Database

SPECIAL ADHOC TEST MODE FOR FUNDAMENTAL CACHE SPEED PATH

IP.com Disclosure Number: IPCOM000007970D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-09
Document File: 3 page(s) / 138K

Publishing Venue

Motorola

Related People

Joseph C. Circello: AUTHOR [+2]

Abstract

In many microprocessors (MPU) with on-chip memories, the cache read path defines a critical speed path. This speed path is shown in the figure, a block diagram of a 2-way, set-associative cache. The path typically begins with the cache address register accessing the tag (also known as the direc- tory) arrays. The tag outputs are compared to the upper address bits to determine if the access "hits" in the cache. The raw hit signals are then combined to form the mux select to gate the appropriate data back to the processor core. Additionally, the raw hit signals form a transfer acknowledge (TA) signal to terminate the cache access in the event of a hit. Finally, the processor core uses the transfer acknowledge signal to form a clock enable signal to load the cache read data into the destination reg- ister. Thus, there are typically two distinct timing arcs of interest: first, the cache transfer acknowl- edge signal factoring into the clock enable for the destination register in the processor core, and sec- ond, the actual cache read data. These paths often are the frequency limiting speed paths for the microprocessor.

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MOTOROLA Technical Developments

SPECIAL ADHOC TEST MODE FOR FUNDAMENTAL CACHE SPEED PATH

by Joseph C. Circello and Anup S. Tirumala

DEFINITION OF THE PROBLEM

  In many microprocessors (MPU) with on-chip memories, the cache read path defines a critical speed path. This speed path is shown in the figure, a block diagram of a 2-way, set-associative cache. The path typically begins with the cache address register accessing the tag (also known as the direc- tory) arrays. The tag outputs are compared to the upper address bits to determine if the access "hits" in the cache. The raw hit signals are then combined to form the mux select to gate the appropriate data back to the processor core. Additionally, the raw hit signals form a transfer acknowledge (TA) signal to terminate the cache access in the event of a hit. Finally, the processor core uses the transfer acknowledge signal to form a clock enable signal to load the cache read data into the destination reg- ister. Thus, there are typically two distinct timing arcs of interest: first, the cache transfer acknowl- edge signal factoring into the clock enable for the destination register in the processor core, and sec- ond, the actual cache read data. These paths often are the frequency limiting speed paths for the microprocessor.

  Prior methodologies relied on verifying this path using functional tests, where an assembly lan- guage program sensitized the speed path and the processor core then executed subsequent instruc- tions to verify the path functioned correctly. One fundamental problem with this approach is that it is difficult and time consuming to distinguish between failures due to the speed path not meeting frequen- cy, versus those due to incorrect operation of the microprocessor. This problem especially manifests itself during the debug of a new MPU.

  This innovation incorporates a special adhoc test mode for verification of the fundamental cache speed path, with minimal interaction with the processor. The special test mode leads to rapid

understanding of the fundamental cache read path for a given frequency, and makes for faster debug- ging and speed-grading of the MPU.

DESCRIPTION OF THE INNOVATION

  Previous Motorola microprocessors made use of a special test mode, named "adhoc", to facilitate testing of on-chip memories. In this test mode, spe- cial logic is enabled to allow direct testing of all on- chip memories via the input/output pins of the device.

  The ColdFire implementation extends this basic concept with an additional test mode called "ADHOC-TA". This new test mode is designed to exercise the same logical path used in the normal functional read operation of the cache, i.e., the cache read operand is loaded into the same des...