Browse Prior Art Database

Method for obtaining dynamic on-chip state for tracing and debug

IP.com Disclosure Number: IPCOM000008013D
Publication Date: 2002-May-10
Document File: 3 page(s) / 18K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for obtaining dynamic on-chip state for tracing and debug. Benefits include improved functionality.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Method for obtaining dynamic on-chip state for tracing and debug

Disclosed is a method for obtaining dynamic on-chip state for tracing and debug. Benefits include improved functionality.

Background

              The conventional method to obtain dynamic processor state does not provide enough details about the processor’s current execution status. Vital information about the translation look-aside buffer (TLB) inserts and faults is not provided.

Description

              The disclosed method obtains the dynamic processor state while it is executing a computer program, referred to as a workload. The state information can be processed into instruction traces useful for performance analysis and debugging. All events that result in the modification of processor control flow are recorded using this method. The performance monitoring counters provide pertinent information about instructions completed by the processor. A dedicated on-chip memory buffer, referred to as history buffer (HB), is defined for storing all the required data. Information about completed instructions can be accessed via a device driver running in kernel mode.

              The primary events responsible for impacting control flow include:

§         Interrupts

§         Faults

§         Thread switches

§         Access to any of the control registers

§         Processor model specific registers

§         Inserts in ITLB/DTLBs 

              For each event, the information required to recreate or understand the cause and impact of that event is stored in the HB.

              For each interruption, fault, and thread switch, two distinct data packets are generated and stored in the HB, a source packet (SP) and a target packet (TP). Each packet contains vital information about the state of the processor at the time of the interruption or fault and a hint for where execution resumed.

              The source and target data packets are both formatted with five fields (see Figures 1 and 2). The Thread ID is of the thread in which the interrupti...