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Method for reduced power by decreasing the number of write ports in register files

IP.com Disclosure Number: IPCOM000008014D
Publication Date: 2002-May-10
Document File: 3 page(s) / 544K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reduced power by decreasing the number of write ports in register files. Benefits include improved power usage.

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Method for reduced power by decreasing the number of write ports in register files

Disclosed is a method for reduced power by decreasing the number of write ports in register files. Benefits include improved power usage.

Background

              Modern processors that execute several instructions in each clock cycle tend to be accompanied by an increased number of register write ports. They increase the size of the register file and its power consumption.

              The increasing number of ports has two major detractors:

§         Increased size: each port requires two wires - one vertical and one horizontal. Additional wires increase the size of the entire register proportionally to the square of the number of wires but with the same number of cells.

§         Increased energy consumption: when a port is added, each wire length is increased linearly (at least, and the increase may be squared for high numbers of wires).

              Figure 1 provides a qualitative look at a conventional register file with two write ports. Figure 2 represents a conventional register file with one write port.

General description

              The disclosed method reduces the number of register write ports to significantly reduce register size and power consumption.  The method maintains multiple copies of the register file, balances the register writes at each clock, and tracks which register contains the updated data at each copy.

      The memory array is duplicated several times. A pointer for each register indicates the copy that contains the most recent information. At each cycle, the num...