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Browse Prior Art Database

CUTOFF DIODE STRUCTURE AS AC IMPROVEMENT

IP.com Disclosure Number: IPCOM000008027D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-13
Document File: 3 page(s) / 143K

Publishing Venue

Motorola

Related People

Robert Meyer: AUTHOR

Abstract

The latest European EMC regulations push the IC market towards more "quiet" devices with reduced electro-magnetic radiation and ground bouncing. A well-known method to reduce ground bounce of CMOS bus driver outputs is to form the NMOS output transistor gate partially in a serpen- tine shape, see Figure 1 for a typical layout scheme and Figure 2 for an example of electrical schemat- ics.

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Page 1 of 3

MOIWROLA Technical Developments

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CUTOFF DIODE STRUCTURE AS AC IMPROVEMENT

FOR SERPENTINED NMOS

by Robert Meyer

BACKGROUND

  The latest European EMC regulations push the IC market towards more "quiet" devices with reduced electro-magnetic radiation and ground bouncing. A well-known method to reduce ground bounce of CMOS bus driver outputs is to form the NMOS output transistor gate partially in a serpen- tine shape, see Figure 1 for a typical layout scheme and Figure 2 for an example of electrical schemat- ics.

output NMOS gate Signal of u&-2

NMOS pre-driver

  As the signal travels through the NMOS transis- tor gate, it will turn on the drain fingers one after another, which reduces the dI/dt coefficient and therefore reduces the ground bounce.

  Most CMOS octal buffers like e.g. AC/HC240/245-type devices are using this or a similar structure. But, this method has several draw- backs:

  a) Propagation delays, especially related to high-impedance-state switching, are increased due to the signal delay.

  b) Transistion times, especially rise times, are increased because the NMOS is turning off signifi- cantly slower.

  c) Cross-switch current, which increases dynamic ICC consumption and VCC bounce, is increased due to the overlap period when the PMOS is already turning on while the NMOS is still par- tially open.

  There is a need to compensate these drawbacks, especially regarding the negative impact on AC parameters depending on the turnoff speedup of the output NMOS transistor. These parameters are typi- cally deteriorated by 15%-25% if gate serpentining is applied to an output NMOS transistor.

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Fig. 1 Layout Scheme

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Fig. 2 Electrical Schematics

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MOTOROLA Technical Developments

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SOLUTION

  The Cutoff diode structure provides a die-size- efficient solution by applying a diode between the output gate pre-driver signal and the remote end of the NMOS output gate, see Figure 3.

  a) All bus drivers are able to switch into "high impedance" mode. This means that there are two states in which the output NMOS transistor has to be cut off: During the low-to-high and the low-to- high-impedance transition. It is not possible to merge these two signals by an "OR" gate, because the delay of the required "OR" gate is in the same range as the time saving achieved by the cutoff tran- sistor, in other words, it becomes useless. The same is true for the solution to connect the gate of the cutoff transistor to the output of the predriver, and inverting the cutoff transistor type: the delay caused by the additional stage is in the same range as the reduction in the output delay time, and therefore eliminating the benefit. Either two cutoff transistors have to be implemented, or only one of the above transitions can be improved.

  b) The cutoff transistor is loading the output gate...