Browse Prior Art Database

LOW DROP OUT REGULATOR WITH NMOS OUTPUT

IP.com Disclosure Number: IPCOM000008033D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2002-May-14
Document File: 2 page(s) / 69K

Publishing Venue

Motorola

Related People

David Susak: AUTHOR

Abstract

The proposed circuit is shown in Figure 1. The intent of this circuit is to provide a regulated volt- age that is insensitive to supply voltage, tempera- ture and processing. The other intent is to supply a regulated voltage that remains within specification as the supply voltage comes near to the regulated voltage.

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MOTOROLA Technical Developments

LOW DROP OUT REGULATOR WITH NMOS OUTPUT

by David Susak

  The proposed circuit is shown in Figure 1. The intent of this circuit is to provide a regulated volt- age that is insensitive to supply voltage, tempera- ture and processing. The other intent is to supply a regulated voltage that remains within specification as the supply voltage comes near to the regulated voltage.

  The basic circuit is an operational amplifier whose input stage is configured as a bandgap refer- ence cell (Q29, 413). The bandgap reference cell has cascade devices to increase output impedance (418, Q5O,Q42, 444). The input stage drives into a Wilson mirror (463, 464, 461, 462). The use of the Wilson mirror maintains balanced currents for the bandgap input stage. The output of the Wilson mirror (462) drives a darlington NF'N output stage which provides gain for the amplifier. The base cur- rent loading affects due to 965 on the input stage are cancelled by 48. The amplifier is compensated

with capacitor C13. The output stage is biased by a current source that is generated via a charge pump. Ripple caused by the charge pump is dampened by the low output impedance of the output stage (Q15, 465). The main output transistor Ml is used to deliver the output load current. Transistor Mls source is the regulated output. If the charge pump can charge high enough (- 1OV above the source of Ml) then the supply voltage (vdd) can drop to with- in a drain-to-source voltage...